VHDL: Unable to read output status

问题

I'm attempting to compile in ModelSim 10.0 and I receive a compile error stating: 'Cannot read output status'.

Here's a snippet of the code. It'd be brilliant if someone could tell me what I'm doing wrong.

entity controller_entity is
generic( entryCount : positive := 2;
         ....);
port(
    clk         : in  std_logic;
    ....
    entry_car_entered : out std_logic_vector(0 to entryCount-1)
);
end entity controller_entity;

architecture controller_v1 of controller_entity is
signal cars_entered : std_logic_vector(0 to entryCount-1);

component entry is
    port(
        clk       : in  std_logic;
        ....
        car_passed: out std_logic  --Output to higher level
    );
end component;

begin   
    CREATE_ENTRANCES: for i in 0 to entryCount-1 generate
                entryi : entry port map(clk => clk,
                        ....
                car_passed => entry_car_entered(i) -- This line causes the problem.                                             

                        end generate CREATE_ENTRANCES;

    .....

);
end architecture controller_v1;

I think I can fix this if I switch to compiling with VHDL 2008 but I'm trying to stick with 1993. Any advice on this issue would be deeply appreciated.

回答1:

VHDL-2008 allows internal use in read of a port in out mode, but previous VHDL versions does not, so based on the error message 'Cannot read output status', and your comment about fixing the problem through use of VHDL-2008, it sounds like this is the problem.

However, the error message may actually be 'Cannot read output "status"', where "status" is a reference to an output named "status" elsewhere in undisclosed code. You may want to search for "status" in all code, to see if a "status" port with mode out is referenced for read.

If so, the problem can be fixed in VHDL-2002 if an internal signal is driven by the component, and the internal signal then drives the out port. This internal signal may then be read internally.

回答2:

A dummy entity/architecture for component entry and commenting out the "..." stuff, add the context clause, and move the port map closing ); to the right place (inside the generate statement):

library ieee;
use ieee.std_logic_1164.all;
entity entry is               -- dummy entry
    port(
        clk       : in  std_logic;
        -- ....
        car_passed: out std_logic  --Output to higher level
    );
end entity;

architecture foo of entry is

begin
    car_passed <= clk; 
end architecture;

library ieee;
use ieee.std_logic_1164.all;

entity controller_entity is
generic( entryCount : positive := 2 --;
         ); --....);
port(
    clk         : in  std_logic;
    -- ....
    entry_car_entered : out std_logic_vector(0 to entryCount-1)
);
end entity controller_entity;

architecture controller_v1 of controller_entity is

    signal cars_entered : std_logic_vector(0 to entryCount-1);

component entry is
    port(
        clk       : in  std_logic;
        -- ....
        car_passed: out std_logic  --Output to higher level
    );
end component;

begin   
CREATE_ENTRANCES: 
    for i in 0 to entryCount-1 generate
entryi: entry 
        port map (
            clk => clk,
                -- ....
            car_passed => entry_car_entered(i) -- This line causes the problem. 
        );
    end generate CREATE_ENTRANCES;

   -- .....

end architecture controller_v1;

And this design specification analyzes, elaborates and simulates with a different VHDL tool 'compliant' to IEEE Std 1076-1993. Your purported error statement is associated with trying to read a port signal or interface list signal of mode out from googling. It's not listed in the Modelsim verror list and has the reported form 'Cannot read the output "signal_name"', noting you don't display a signal name of status.

There are several possibilities. There's a defect in the version of Modelsim you are using to the effect the error message is erroneous (and has been subsequently removed) or your code snippet doesn't accurately reflect your design specification or where the error actually is. Perhaps the error message comes from something else or my verror list is inaccurate.

In any event you could use a signal declared in architecture controller_v1 connected to generated instantiated entry components port car_passed , and assign it to the output port signal entry_car_entered. You could do that element by element of entry_car_entered in the generate statement more than likely.

If you have an error number associated with a Modelsim error it's possible to get an expanded description of the error with verror. The expanded description generally provides enough information to correct an issue.

来源：https://stackoverflow.com/questions/22120218/vhdl-unable-to-read-output-status

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compiler-errors

vhdl

modelsim