问题
I'm trying to simulate ICE5LP1K FPGA internal oscillator on ModelSim. My design includes the following instance:
SB_HFOSC OSCInst1 (
.CLKHFEN(1'b1),
.CLKHFPU(1'b1),
.CLKHF(CLKLF)
)
I included sb_ice_syn.v file but have a design loading error:
Error: ../testbench/sb_ice_syn.v(26066): Module 'SB_HFOSC_CORE' is not defined
I'm not able to find SB_HFOSC_CORE module in the lattice installation folder. Where can I find the missed modules?
回答1:
Doing ModelSim simulation of a Lattice ICE40 family (ICE5LP1K device) design with PLLs requires that a Verilog model of the PLL is included. This is described in Lattice Application Note AN006 (see "c:\lscc\iCEcube2.2015.04\doc\Modelsim_AN006.pdf" for latest iCEcube2 version) on page 9:
If your design contains PLL, add ABIPTBS8.v and ABIWTCZ4.v in $INST_DIR/verilog. For performing Post-Synth simulation for a VHDL design having PLL, you will require a mixed-language simulator, since the PLL model (ABIPTBS8.v) is available only in verilog format. If the design contains Hardened IP primitives, add the encrypted Verilog simulation library sb_ice_ipenc_modelsim.v available in $INST_DIR/Verilog.
An alternative is if you write a simple simulation model of the SB_HFOSC_CORE PLL core, and then include this in the simulation, since I assume that your focus is on verification of the remaining design, so you probably only need the PLL to give a usable clock.
回答2:
It is working now. I found the missing module in the sb_ice_ipenc_modelsim.v
来源：https://stackoverflow.com/questions/32524308/lattice-fpga-internal-oscillator-simulation-issues