micro-optimization

问题 A following-up question for Why does this `std::atomic_thread_fence` work As a dummy interlocked operation is better than _mm_mfence , and there are quite many ways to implement it, which interlocked operation and on what data should be used? Assume using an inline assembly that is not aware of surrounding context, but can tell the compiler which registers it clobbers. 回答1: Short answer for now, without going into too much detail about why. See specifically the discussion in comments on that

问题 A following-up question for Why does this `std::atomic_thread_fence` work As a dummy interlocked operation is better than _mm_mfence , and there are quite many ways to implement it, which interlocked operation and on what data should be used? Assume using an inline assembly that is not aware of surrounding context, but can tell the compiler which registers it clobbers. 回答1: Short answer for now, without going into too much detail about why. See specifically the discussion in comments on that

问题 It is generally understood that one store buffer entry is allocated per store, and this store buffer entry holds the store data and physical address 1 . In the case that a store crosses a 4096-byte page boundary, two different translations may be needed, one for each page, and hence two different physical addresses may need to be stored. Does this mean that page-crossing stores take 2 store buffer entries? If so, does it apply also to line-crossing stores? 1 ... and perhaps some/all of the

问题 The issue of the repz ret has been covered here [1] as well as in other sources [2, 3] quite satisfactorily. However, reading neither of these sources, I found answers to the following: What is the actual penalty in a quantitative comparison with ret or nop; ret ? Especially in the latter case – is decoding one extra instruction (and an empty one at that!) really relevant, when most functions either have 100+ of those or get inlined? Why did this never get fixed in AMD K8, and even made its

问题 I just found code that prepends with substr( $str, 0, 0, $prepend ) my $foo = " world!" substr( $foo, 0, 0, "Hello " ); Is this any faster than my $foo = " world!" $foo = "Hello $foo"; 回答1: Optrees If we compare the two optrees the top has b <@> substr[t2] vK/4 ->c - <0> ex-pushmark s ->7 7 <0> padsv[$foo:2,3] sM ->8 8 <$> const[IV 0] s ->9 9 <$> const[IV 0] s ->a a <$> const[PV "Hello "] s ->b While the bottom has 8 <+> multiconcat(" world!",-1,7)[$foo:2,3] sK/TARGMY,STRINGIFY ->9 - <0> ex

问题 Closed. This question needs debugging details. It is not currently accepting answers. Want to improve this question? Update the question so it's on-topic for Stack Overflow. Closed 2 years ago . I'm currently working on some optimizations and comparing vectorization possibilities for DSP applications, that seem ideal for AVX512, since these are just simple uncorrelated array processing loops. But on a new i9 I didn't measure any reasonable improvements when using AVX512 compared to AVX2. Any

问题 If we have an array of integer pointers which all pointing to the same int, and loop over it doing ++ operation, it'll be 100% slower than those pointers pointing to two different ints. Here is a concrete example int* data[2]; int a, b; a = b = 0; for (auto i = 0ul; i < 2; ++i) { // Case 3: 2.5 sec data[i] = &a; // Case 2: 1.25 sec // if (i & 1) // data[i] = &a; // else // data[i] = &b; } for (auto i = 0ul; i < 1000000000; ++i) { // Case 1: 0.5sec // asm volatile("" : "+g"(i)); // deoptimize

问题 If we have an array of integer pointers which all pointing to the same int, and loop over it doing ++ operation, it'll be 100% slower than those pointers pointing to two different ints. Here is a concrete example int* data[2]; int a, b; a = b = 0; for (auto i = 0ul; i < 2; ++i) { // Case 3: 2.5 sec data[i] = &a; // Case 2: 1.25 sec // if (i & 1) // data[i] = &a; // else // data[i] = &b; } for (auto i = 0ul; i < 1000000000; ++i) { // Case 1: 0.5sec // asm volatile("" : "+g"(i)); // deoptimize

问题 To multiply a number by any any multiple of 2, I'll shift it those many times. Is there any such technique to multiply a number by 10 in less cycles? 回答1: The 80286 did not have a barrel shifter, that was introduced with the 80386. According to the timing tables in the Microsoft Macro Assembler 5.0 documentation (1987), SHL reg, immed8 takes 5+n cycles, whereas SHL reg, 1 takes 2 cycles. ADD reg, reg takes 2 cycles, as does MOV reg, reg . IMUL reg16, immed takes 21 cycles. Therefore, the

问题 To multiply a number by any any multiple of 2, I'll shift it those many times. Is there any such technique to multiply a number by 10 in less cycles? 回答1: The 80286 did not have a barrel shifter, that was introduced with the 80386. According to the timing tables in the Microsoft Macro Assembler 5.0 documentation (1987), SHL reg, immed8 takes 5+n cycles, whereas SHL reg, 1 takes 2 cycles. ADD reg, reg takes 2 cycles, as does MOV reg, reg . IMUL reg16, immed takes 21 cycles. Therefore, the