memory-segmentation

After quite a bit of googling and some hints given here , I finally managed to find a layout of the FS segment (used by windows to store TIB data). Of particular interest to me is the ArbitraryUserPointer member provided in the PSDK: typedef struct _NT_TIB { struct _EXCEPTION_REGISTRATION_RECORD *ExceptionList; PVOID StackBase; PVOID StackLimit; PVOID SubSystemTib; union { PVOID FiberData; DWORD Version; }; PVOID ArbitraryUserPointer; struct _NT_TIB *Self; } NT_TIB; How safe exactly is it to use this variable (under Vista and above)? and does it still exist on x64? Secondary to that is the

I needed to know if there is any restriction on loading code segment registers directly by using mov instructions . This struck me while going through the switching from real mode to protected mode . I found that in order to put the correct value in the code segment "jump" instruction is used to set the correct segment . So is this usage of jump instruction owing to any such restriction ? Why cannot we directly load a value into the code segment ? Setting CS would be a jump, because code-fetch happens from CS:IP (or CS:RIP/EIP). It makes sense that doing this is restricted to jmp far / call

I Googled for a long time but I still don't understand how it works as most of the explanation are very technical and there are no illustrations to make it clearer. My primary confusion is that what is its'difference with virtual memory? I hope this question will have a very good explanation here so that other people who ask the same question can find it here when they Google it. I have to admit, those two concepts can seem quite complicated and similar at the beginning. Sometimes they are also taught confusingly. A good reference in my opinion can be found on osdev.org: Segmentation Paging

I can calculate an address Segment:Offset as Segment * 0x10 + Offset . But how do I calculate the opposite? E.g. how do I get from 0xF4170 to F400:0170 and from 0xACF04 to ABCD:1234 ? Necrolis You would be required to have either the base or the offset to start with, along with the linear address, as multiple Segment:Offset pairs can map to the same linear address. so if we have the segment 0xF400 and the linear address 0xF4170 , we get the offset being 0xF4170 - (0xF400 << 4) which is 0x170 . Doing this with only knowing the linear address doesn't have a unique solution, so you have to choose

According to AMD manual segmentation can not be disabled. My question is why, why it's impossible? Another question, it says that 64-bit disables it, what does that mean? Is segmentation completly disabled on 64-bit mode? AMD Manual: https://s7.postimg.cc/hk15o6swr/Capture.png Introduction In 64-bit mode, whenever a non-null segment selector is loaded into any of the segment registers, the processor automatically loads the corresponding segment descriptor in the hidden part of the segment register, just like in protected/compatibility mode. However, the segment descriptors selected by the DS,

x86 CPUs have had all kinds of tricky modes and memory segmentation over the generations from 16-bit to 32-bit to 64-bit. These days with modern OSes using modern CPUs in modern operating modes you don't have to worry about memory segments, but you can still run legacy apps on legacy OSes on the modern CPUs, in which case I presume the CPUs run in a special legacy mode (protected mode, real mode, etc). So obviously the segment registers exist for reasons of backward compatibility, but is that the only reason? Are there modern uses for the segment registers too? Or have they just become general

I am studying computer architecture from the Intel Manual. The thing that I understand is that the instructions that we give are logical addresses which consist of a segment selector and an offset. It is basically CS register<<4 + offset . The Segment Selector maps to the GDT or LDT as given in the TI bit of the segment selector. GDT consists of Segment Descriptors which have BASE , LIMIT and RPL and the output is base address. This base address + offset provides the logical address . What are the rules that decide which segment register ( SS , DS , etc.) applies to different memory operations