memory-segmentation

Can someone help me with segmentation and 8086 intel's microprocessor?

独自空忆成欢 提交于 2020-01-05 05:09:12
问题 I am reading about the architecture of intel's 8086 and can't figure out the following things about segmentation: I know that segment registers point to segments respectively and contain the base address of a 64kb long segment. But who calculates and in which point sets the physical address in the segment registers? Also, because one physical address can be accessed by multiple segment:offset pairs and segments can overlap, how you can be sure that you won't overwrite something? Where I can

Does C have an equivalent of std::less from C++?

不想你离开。 提交于 2020-01-01 23:13:33
问题 I was recently answering a question on the undefined behaviour of doing p < q in C when p and q are pointers into different objects/arrays. That got me thinking: C++ has the same (undefined) behaviour of < in this case, but also offers the standard library template std::less which is guaranteed to return the same thing as < when the pointers can be compared, and return some consistent ordering when they cannot. Does C offer something with similar functionality which would allow safely

What is segmentation and paging in Computer Science?

痞子三分冷 提交于 2019-12-21 20:38:52
问题 I Googled for a long time but I still don't understand how it works as most of the explanation are very technical and there are no illustrations to make it clearer. My primary confusion is that what is its'difference with virtual memory? I hope this question will have a very good explanation here so that other people who ask the same question can find it here when they Google it. 回答1: I have to admit, those two concepts can seem quite complicated and similar at the beginning. Sometimes they

Do the x86 segment registers have special meaning/usage on modern CPUs and OSes?

我的未来我决定 提交于 2019-12-20 02:14:12
问题 x86 CPUs have had all kinds of tricky modes and memory segmentation over the generations from 16-bit to 32-bit to 64-bit. These days with modern OSes using modern CPUs in modern operating modes you don't have to worry about memory segments, but you can still run legacy apps on legacy OSes on the modern CPUs, in which case I presume the CPUs run in a special legacy mode (protected mode, real mode, etc). So obviously the segment registers exist for reasons of backward compatibility, but is that

virtual memory concepts

前提是你 提交于 2019-12-19 11:40:16
问题 I am confused about some topics regarding virtual memory. So, i am going to pointwise list them and ask questions. While answering i will prefer if you also list some source where i can clear that doubt. I will be talking with reference to a linux elf executable file. I have heard that every process has the address space of 4gb in a 32 bit system. When i checked the objdump of one of my executable relocatable file i saw that it had limits from 00000000 to ffffffff. Also it contained the

What will be the output of this? Please explain it also [closed]

筅森魡賤 提交于 2019-12-13 23:25:29
问题 Closed. This question is off-topic. It is not currently accepting answers. Want to improve this question? Update the question so it's on-topic for Stack Overflow. Closed 5 years ago . #include<stdio.h> int main(){ int a; printf("%u\n ",&a); printf("%p\n ",a); printf("%p\n ",&a); printf("%fp\n ",&a); return 0; } I have tried this code but I am not able to understand the output 4193177020 (nil) 0x7ffff9eecdbc 0.000000p What is semgmented memory address in this and what part is offset? 回答1:

Does CS:IP use the MSROM?

别来无恙 提交于 2019-12-11 14:25:54
问题 Does CS:IP use the MSROM? Because it needs to decode to an instruction that checks the segment cache to see whether or not it is present and instructions to read the segment base from the cache, otherwise it jumps to instructions that fetch it from memory and perform the address calculation. Otherwise I suppose it could be done by the AGU and it gets decoded to something that the AGU recognises. If this were the case then the AGU would have to have the ability to insert loads in the load

TIB Custom Storage

别来无恙 提交于 2019-12-10 11:28:59
问题 After quite a bit of googling and some hints given here, I finally managed to find a layout of the FS segment (used by windows to store TIB data). Of particular interest to me is the ArbitraryUserPointer member provided in the PSDK: typedef struct _NT_TIB { struct _EXCEPTION_REGISTRATION_RECORD *ExceptionList; PVOID StackBase; PVOID StackLimit; PVOID SubSystemTib; union { PVOID FiberData; DWORD Version; }; PVOID ArbitraryUserPointer; struct _NT_TIB *Self; } NT_TIB; How safe exactly is it to

How to use a logical address in gdb?

不问归期 提交于 2019-12-10 01:23:41
问题 gdb provides functionality to read or write to a specific linear address , for example: (gdb) x/1wx 0x080483e4 0x80483e4 <main>: 0x83e58955 (gdb) but how do you specify a logical address ? I came accross the following instruction: 0x0804841a <+6>: mov %gs:0x14,%eax how can i read the memory at "%gs:0x14" in gdb, or translate this logical address to a linear address that i could use in x command ? note: i know that i could simply read %eax after this instruction, but that is not my concern 回答1

Why can't mov set CS, the code segment register, even though it can set others?

大城市里の小女人 提交于 2019-12-07 16:47:23
问题 I needed to know if there is any restriction on loading code segment registers directly by using mov instructions . This struck me while going through the switching from real mode to protected mode . I found that in order to put the correct value in the code segment "jump" instruction is used to set the correct segment . So is this usage of jump instruction owing to any such restriction ? Why cannot we directly load a value into the code segment ? 回答1: Setting CS would be a jump, because code