flip-flop | 易学教程

FSM for long bit sequence

阅读更多关于 FSM for long bit sequence

问题 Currently, I'm working on a mealy fsm that detects a 17 bit sequence 10100001010000001. Due to the length of the sequence, I'm having difficulty figuring out which state to return to when the input doesn't allow me to move on to the next state. Any suggestions ?? 来源： https://stackoverflow.com/questions/60181822/fsm-for-long-bit-sequence

When would a Ruby flip-flop be useful?

阅读更多关于 When would a Ruby flip-flop be useful?

问题 I think I understand how a flip-flop works thanks to a tutorial, but the example there is contrived just for teaching. Can anyone give an example of how you have actually used or would use a flip-flop? I'm looking for a real-world application, not just another demonstration. What problems can this tool solve? The link used to be http://vision-media.ca/resources/ruby/ruby-flip-flop-or-range-operators , but seems to be spam this days. 回答1: Here's an example (taken from a rubycentral.com article

How many Flip Flops will this code produce?

阅读更多关于 How many Flip Flops will this code produce?

问题 so I have an exam coming up and I am solving tutes. One of the questions is very basic but I don't think I have the exact logic down for it. It simply gives me a small bit of the code and asks how many Flip Flops will this produce. Could you help me understand how I can find this out? Thanks! Architecture rtl of ex is signal a,b,q, int: bit_vector(3 downto 0); begin process(clk) begin If clk = '1' and clk'event then int <= int +1; q <=int; a <= b xor q; end if; end process; b <= int end; 回答1:

Verilog 4-bit up-down counter designed using negative edge triggered T flip flops

阅读更多关于 Verilog 4-bit up-down counter designed using negative edge triggered T flip flops

问题 I'm very new to Verilog HDL and I have to code this 4bit up down counter. With the help of some reading on up-down counters and t flipflops, I already made the following code: module up_down_4bitcounter ( out, up_down, clk, data, reset ); //Output Ports output [3:0] out; //Input Ports input [3:0] data; input up_down, clk, reset; //Internal Variables reg [3:0] out; //Start of Code always @(negedge clk) if (reset) begin // active high reset out <= 4'b0 ; end else if (up_down) begin out <= out +

Minimal number of D flip-flops

阅读更多关于 Minimal number of D flip-flops

问题 I have encountered the following question and can't be sure on the answer. Do you have any suggestions, any help would be much appreciated. The Fibonacci sequence F(n) is defined by F(1)=1, F(2)=1, and Fn=F(n-2) + F(n-1) for all integers n>= 3. What is the minimal number of D flip-flops required (along with combinational logic) to design a counter circuit that outputs the first seven Fibonacci numbers (i.e., F1 through F7 ) and then wraps around? (A) 3 (B) 4 (C) 5 (D) 6 (E) 7 Thanks in

Undefined output of Ring Counter Test waveform

阅读更多关于 Undefined output of Ring Counter Test waveform

问题 I have modeled 4 bit Ring Counter using D Flip Flop. The D flip flop is in separate file, included in my workspace. The D flip flop works correctly (gives correct output waveform). This is the code of ring counter: library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity ring4counter is port ( clk: std_logic; output: out std_logic_vector(3 downto 0)); end ring4counter; architecture ring4counter_arch of ring4counter is component dff port ( clk: std_logic; d: in std

Why does a Flip-Flop operator include the second condition?

阅读更多关于 Why does a Flip-Flop operator include the second condition?

问题 The following code is using a flip-flop operator. (1..10).each {|x| print "#{x}," if x==3..x==5 } Why are the results 3,4,5 ? I think it should be 3,4 . As mentioned in a tutorial, this expression becomes true when x == 3 , and continues to be true until x == 5 . How could '5' been printed if it evaluates to false? Could anyone please clarify that for me? 回答1: The important link, from "The Ruby Programming Language" is : 4.6.9.1 Boolean flip-flops When the .. and ... operators are used in a

Verilog D-Flip-Flop not re-latching after asynchronous reset

阅读更多关于 Verilog D-Flip-Flop not re-latching after asynchronous reset

问题 I have a flip-flop with an asynchronous reset and an enable. Here is my code: module DFF_aSR(in, enable, clock, reset, out); input in, enable, clock, reset; output out; reg out; always @ (posedge clock or posedge reset) begin if (reset) begin out <= 1'b0; end else if (enable) begin out <= in; end end endmodule But here is my resulting waveform, which shows that the relatch is not happening after the reset, why is this so? 回答1: The latch output should go high if/when a rising clock edge occurs

Verilog D-Flip-Flop not re-latching after asynchronous reset

阅读更多关于 Verilog D-Flip-Flop not re-latching after asynchronous reset

I have a flip-flop with an asynchronous reset and an enable. Here is my code: module DFF_aSR(in, enable, clock, reset, out); input in, enable, clock, reset; output out; reg out; always @ (posedge clock or posedge reset) begin if (reset) begin out <= 1'b0; end else if (enable) begin out <= in; end end endmodule But here is my resulting waveform, which shows that the relatch is not happening after the reset, why is this so? The latch output should go high if/when a rising clock edge occurs with data stable high and reset stable low. The only such edge I see is before the first reset pulse. If

Is Perl's flip-flop operator bugged? It has global state, how can I reset it?

阅读更多关于 Is Perl's flip-flop operator bugged? It has global state, how can I reset it?

I'm dismayed. OK, so this was probably the most fun Perl bug I've ever found. Even today I'm learning new stuff about Perl. Essentially, the flip-flop operator .. which returns false until the left-hand-side returns true , and then true until the right-hand-side returns false keep global state (or that is what I assume.) Can I reset it (perhaps this would be a good addition to Perl 4-esque hardly ever used reset() )? Or, is there no way to use this operator safely? I also don't see this (the global context bit) documented anywhere in perldoc perlop is this a mistake? Code use feature ':5.10';