Verilog D-Flip-Flop not re-latching after asynchronous reset

问题

I have a flip-flop with an asynchronous reset and an enable. Here is my code:

module DFF_aSR(in, enable, clock, reset, out);
input in, enable, clock, reset;
output out;
reg out;

always @ (posedge clock or posedge reset) begin
    if (reset) begin
        out <= 1'b0;
    end 
    else if (enable) begin
        out <= in;
    end 
end
endmodule

But here is my resulting waveform, which shows that the relatch is not happening after the reset, why is this so?

回答1:

The latch output should go high if/when a rising clock edge occurs with data stable high and reset stable low. The only such edge I see is before the first reset pulse. If you wish for the latch to grab a signal at e.g. time 110ns, you should ensure that the reset input goes low prior to that. If your intention is that reset should be edge-triggered rather than level triggered, you may need to use a pair of flops, one triggered by clock and the other by reset, wired such that the D output of the first connects to Q of the second, and D of the second connects to /Q of the first. Feeding the outputs of the latches into an XOR gate will yield a signal that will indicate which signal had the most recent rising edge (warning: simultaneous rising edges may trigger metastability). The signal you seem to want could then be formed by taking the "AND" of the latched data with the output of the XOR, along with possibly some hazard-avoidance gates.

来源：https://stackoverflow.com/questions/28161128/verilog-d-flip-flop-not-re-latching-after-asynchronous-reset