Creating a Register File with a Test Bench

问题

So I would like to simulate a simple register file and test it. But it's been pretty confusing. I put together what I hope is a functional register file based on the notes that my professor provided, but now I'm struggling to create the test bench for it. I guess the main thing is how it has two DATA's and ADDR's (he showed an example of a memory file which only has one of each).

Anyway, for my test bench I simply want to write some numbers to the register like in a for loop and instantiate register1 to 1, register2 to 2, and so on up to 32. After that I want to read it back to make sure everything is correct.

Here's what I have so far:

Register_File

`include "prj_definition.v"
module REGISTER_FILE_32x32(DATA_R1, DATA_R2, ADDR_R1, ADDR_R2, 
                            DATA_W, ADDR_W, READ, WRITE, CLK, RST);

// input list
input READ, WRITE, CLK, RST;
input [`DATA_INDEX_LIMIT:0] DATA_W;
input [`REG_ADDR_INDEX_LIMIT:0] ADDR_R1, ADDR_R2, ADDR_W;

// output list
output [`DATA_INDEX_LIMIT:0] DATA_R1;
output [`DATA_INDEX_LIMIT:0] DATA_R2;

reg [`DATA_INDEX_LIMIT:0] data_ret; // return data register 
integer i; // index for reset opeations

reg [`DATA_INDEX_LIMIT:0] DATA_R1;
reg [`DATA_INDEX_LIMIT:0] DATA_R2;
reg [`DATA_INDEX_LIMIT:0] sram_32x32m [0:`MEM_INDEX_LIMIT]; // memory storage

// Parameter for the memory initialization file name
parameter mem_init_file = "mem_content_01.dat";

assign DATA_W = ((READ===1'b1)&&(WRITE===1'b0))?DATA_R1:{`DATA_WIDTH{1'bz} }; //drives the bus during read operation
assign DATA_W = ((READ===1'b1)&&(WRITE===1'b0))?DATA_R2:{`DATA_WIDTH{1'bz} }; //drives the bus during read operation

initial 
begin
DATA_R1 = {`DATA_WIDTH{1'b0} }; //initializing content of all 32 registers as 0
DATA_R2 = {`DATA_WIDTH{1'b0} }; //initializing content of all 32 registers as 0
for(i = 0;i <= `MEM_INDEX_LIMIT; i = i + 1) //up to 32
    sram_32x32m[i] = {`DATA_WIDTH{1'b0}};

end

always @ (negedge RST or posedge CLK)
begin
// TBD: Code for the register file model
if (RST === 1'b0)
begin
for(i = 0;i <= `MEM_INDEX_LIMIT; i = i + 1) //up to 32
    sram_32x32m[i] = {`DATA_WIDTH{1'b0}};

$readmemh(mem_init_file, sram_32x32m);
end
else
begin
 if ((READ===1'b1)&&(WRITE===1'b0))// for read operation
 begin 
    DATA_R1 =  sram_32x32m[ADDR_R1];
    DATA_R2 =  sram_32x32m[ADDR_R2];
 end
 else if ((READ===1'b0)&&(WRITE===1'b1)) // for write operation
    sram_32x32m[ADDR_W] = DATA_W;
end
end
endmodule

register_file_tb

`include "prj_definition.v"
module REGISTER_FILE_TB;

// Storage list
reg [`ADDRESS_INDEX_LIMIT:0] ADDR_R1;
reg [`ADDRESS_INDEX_LIMIT:0] ADDR_R2;
reg [`ADDRESS_INDEX_LIMIT:0] DATA_W;
reg [`ADDRESS_INDEX_LIMIT:0] ADDR_W;

// reset
reg READ, WRITE, RST;

// data register
reg [`DATA_INDEX_LIMIT:0] DATA_REG;
integer i; // index for memory operation
integer no_of_test, no_of_pass;
integer load_data;

// wire lists
wire  CLK;
wire [`DATA_INDEX_LIMIT:0] DATA_R1;
wire [`DATA_INDEX_LIMIT:0] DATA_R2;

assign DATA_R1 = ((READ===1'b0)&&(WRITE===1'b1))?DATA_REG:{`DATA_WIDTH{1'bz} }; //drives the bus during write operation
assign DATA_R2 = ((READ===1'b0)&&(WRITE===1'b1))?DATA_REG:{`DATA_WIDTH{1'bz} }; //drives the bus during write operation

// Clock generator instance
CLK_GENERATOR clk_gen_inst(.CLK(CLK));

// register instantiation
REGISTER_FILE reg_inst(.DATA_R1(DATA_R1), .DATA_R2(DATA_R2), .ADDR_R1(ADDR_R1), .ADDR_R2(ADDR_R2), 
    .DATA_W(), .ADDR_W(), .READ(READ), .WRITE(WRITE), .CLK(CLK), .RST(RST));
endmodule

Thanks in advance for your help!

来源：https://stackoverflow.com/questions/29424930/creating-a-register-file-with-a-test-bench

标签

verilog

system-verilog

modelsim