verilog

问题 Is it possible to use VHDL-2008 hierarchical references / external names to reference Verilog nets? Questa Sim (10.6c) stops the simulation with this error message: vsim-8509: The object class "SIGNAL" of "dut_i.my_net" is different from the class "net" of the denoted object. Here's the VHDL code that fails: alias my_alias is << signal dut_i.my_net : std_logic >>; 回答1: According to the Questa User Manual: Questa SIM supports the IEEE 1076-2008 standard “external name” syntax that allows you

问题 While I was trying to run the simulation in vivado, I got: ERROR: Iteration limit 10000 is reached. Possible zero delay oscillation detected where simulation time can not advance. Please check your source code. Note that the iteration limit can be changed using switch -maxdeltaid. Time: 10 ns Iteration: 10000 I don't have any initial statement in my module being tested. Could anybody point out where the problem could be? `timescale 1ns / 1ps module mulp( input clk, input rst, input start,

问题 I wrote a simple block like this, but the cnt value is changed arbitrarily. The result is not supposed to change with size of cnt, but actually it is. always @* begin cnt = 0; $display(" Now cnt is reset as %d", cnt); for (i = 0; i < IN_NUM; i = i+1)begin $display ("x[i] ~^ w[i] value: %d ", (x[i] ~^ w[i])); $display ("Count value before: %d ", cnt); cnt = cnt + (x[i] ~^ w[i]); $display ("Count value after: %d ", cnt); end end The console result is: Now cnt is reset as 0 x[i] ~^ w[i] value: 1

问题 I wrote a simple block like this, but the cnt value is changed arbitrarily. The result is not supposed to change with size of cnt, but actually it is. always @* begin cnt = 0; $display(" Now cnt is reset as %d", cnt); for (i = 0; i < IN_NUM; i = i+1)begin $display ("x[i] ~^ w[i] value: %d ", (x[i] ~^ w[i])); $display ("Count value before: %d ", cnt); cnt = cnt + (x[i] ~^ w[i]); $display ("Count value after: %d ", cnt); end end The console result is: Now cnt is reset as 0 x[i] ~^ w[i] value: 1

问题 I wrote a simple block like this, but the cnt value is changed arbitrarily. The result is not supposed to change with size of cnt, but actually it is. always @* begin cnt = 0; $display(" Now cnt is reset as %d", cnt); for (i = 0; i < IN_NUM; i = i+1)begin $display ("x[i] ~^ w[i] value: %d ", (x[i] ~^ w[i])); $display ("Count value before: %d ", cnt); cnt = cnt + (x[i] ~^ w[i]); $display ("Count value after: %d ", cnt); end end The console result is: Now cnt is reset as 0 x[i] ~^ w[i] value: 1

问题 I'm trying to make a counter that counts from 0-9 and displays on my Nexys A7's seven segment display. The code compiles, but in the testbench it shows that all the outputs are unknown. I tested my clock divider module, and it looks fine. I'm not sure why it isn't working. module BCD_sevenseg( input clk, output segA, segB, segC, segD, segE, segF, segG, segDP, div_clk ); counter module1( .clk(clk), .div_clk(div_clk) ); reg[3:0] BCD; //BCD signal is 4 bits wide always@(posedge clk) //check

问题 when I try to write to a[b+1] where the bits of b are all '1' ,the value of the reg a[0] do not update,but when I try a[b+1'b1],it updated awaddr_wa <= awaddr_wa + 2; awaddr[awaddr_wa] <= AWADDR_M; awlen [awaddr_wa] <= 4'd0; awaddr[awaddr_wa+6'd1] <= AWADDR_M+16; awlen [awaddr_wa+6'd1] <= 4'd0 so ,why? 回答1: Here is a reproducible example: module M; integer a[0:7] = {0,1,2,3,4,5,6,7}; reg [2:0] b = -1; initial begin $display("a[b+1]=", a[b+1]); $display("a[b+1'b1]=", b+1'b1); end endmodule

问题 When incompletely assigning a value I get a latch. But why did I get a latch in the example below? I think there is no need for the latch of F output because it is defined at all values of SEL . Verilog code: always @ (ENB or D or A or B pr SEL) if (ENB) begin Q=D; if (SEL) F=A; else F=B; end Inferred logic: 回答1: Although it is defined at all values of SEL , it is not defined for all values of ENB . If ENB = 0 , your code says that both Q and F should hold the value from the previous cycle.

问题 I have an array that I want to load up from a binary file: parameter c_ROWS = 8; parameter c_COLS = 16; reg [15:0] r_Image_Raw[0:c_ROWS-1][0:c_COLS-1]; My input file is binary data, 256 bytes long (same total space as r_Image_Raw). I tried using $fread to accomplish this, but it only works through the 4th column of the last row: n_File_ID = $fopen(s_File_Name, "r"); n_Temp = $fread(r_Image_Raw, n_File_ID); I also tried using $fscanf for this, but I get an error about packed types when opening

问题 I have an array that I want to load up from a binary file: parameter c_ROWS = 8; parameter c_COLS = 16; reg [15:0] r_Image_Raw[0:c_ROWS-1][0:c_COLS-1]; My input file is binary data, 256 bytes long (same total space as r_Image_Raw). I tried using $fread to accomplish this, but it only works through the 4th column of the last row: n_File_ID = $fopen(s_File_Name, "r"); n_Temp = $fread(r_Image_Raw, n_File_ID); I also tried using $fscanf for this, but I get an error about packed types when opening