Incomplete assignment and latches
问题 When incompletely assigning a value I get a latch. But why did I get a latch in the example below? I think there is no need for the latch of F output because it is defined at all values of SEL . Verilog code: always @ (ENB or D or A or B pr SEL) if (ENB) begin Q=D; if (SEL) F=A; else F=B; end Inferred logic: 回答1: Although it is defined at all values of SEL , it is not defined for all values of ENB . If ENB = 0 , your code says that both Q and F should hold the value from the previous cycle.