system-verilog

问题 I am creating UVM VIP which is able to switch its clock polarity. Clocking block is used in the interface. For example, a monitor should sample the data using posedge or negedge of incoming clock depending on UVM configuration - and this polarity change can happen on the fly. This can be implemented as follows: // In the interface, two clocking blocks are defined // one for posedge (passive_cb), one for negedge (passive_cbn). task wait_clock_event(); if (cfg.pol == 0) @vif.passive_cb; else

问题 Is it possible to exclude some coverpoints from a particular group based on a parameter? covergroup NEW (string for_exclusion) @ (clk); option.per_instance = 1; option.comment = for_exclusion; apples: coverpoint (available) { bins hit1 = {1'b1};} bananas: coverpoint ({not_available, less}) {bins hit1 = {1'b1};} oranges: coverpoint ({available, less}) {bins hit1 = {1'b1};} rose: coverpoint ({available, flower}) {bins hit1 = {1'b1};} This is small part of the original file. I want to exclude

问题 I have an array that I want to load up from a binary file: parameter c_ROWS = 8; parameter c_COLS = 16; reg [15:0] r_Image_Raw[0:c_ROWS-1][0:c_COLS-1]; My input file is binary data, 256 bytes long (same total space as r_Image_Raw). I tried using $fread to accomplish this, but it only works through the 4th column of the last row: n_File_ID = $fopen(s_File_Name, "r"); n_Temp = $fread(r_Image_Raw, n_File_ID); I also tried using $fscanf for this, but I get an error about packed types when opening

问题 I have an array that I want to load up from a binary file: parameter c_ROWS = 8; parameter c_COLS = 16; reg [15:0] r_Image_Raw[0:c_ROWS-1][0:c_COLS-1]; My input file is binary data, 256 bytes long (same total space as r_Image_Raw). I tried using $fread to accomplish this, but it only works through the 4th column of the last row: n_File_ID = $fopen(s_File_Name, "r"); n_Temp = $fread(r_Image_Raw, n_File_ID); I also tried using $fscanf for this, but I get an error about packed types when opening

问题 the code doesn't Works. I am getting "Malformed statement" error. Can you guys help me? it appears in ring_c1 module instantiation. Thanks in advance. module log2(N,clk); `include "parameters.vh" input [7:0] N; reg [7:0] aux ; reg [7:0] last_log; reg [7:0] div_last; output reg [7:0] y; // assign aux = N; input clk; parameter high = 1; always @ (posedge clk) begin ring_c1 ri1 ( aux[0], div_last); aux = aux >> 1; if (aux < 1 ) begin ring_c1 r1v ( high, div_last); log_Finale (last_log, div_last)

问题 I'm using systemVerilog and I have a package that holds some of my modules parameter values (for example parameter SPI_RATE = 2_000_000; ). Is there any way I can set one value for simulation and a different one for synthesis? (I'm using ModelSim). For example I would like something like: if(IN_SIM) begin parameter SPI_RATE = 2_000_000; end else begin parameter SPI_RATE = 1_000_000; end Thanks! 回答1: Yes, that's possible. SystemVerilog supports conditional compiler directives such as `ifdef ,

问题 This was an interview question asked by a top 10 company of US. Code 1: always @(a or b or sel) begin if (sel == 1) c = a; else if (sel == 0) c =b; end This will create a mux. Code 2: Now "SEL" is removed from sensitivity. Will it still create mux? For the code below? If not, what logic will be created? always @(a or b) begin if (sel == 1) c = a; else if (sel == 0) c =b; end 回答1: Yes, this will still synthesize to a multiplexer 1 . A synthesis tool will interpret this RTL as if the

问题 This was an interview question asked by a top 10 company of US. Code 1: always @(a or b or sel) begin if (sel == 1) c = a; else if (sel == 0) c =b; end This will create a mux. Code 2: Now "SEL" is removed from sensitivity. Will it still create mux? For the code below? If not, what logic will be created? always @(a or b) begin if (sel == 1) c = a; else if (sel == 0) c =b; end 回答1: Yes, this will still synthesize to a multiplexer 1 . A synthesis tool will interpret this RTL as if the

问题 In top.v, I generate X_MAX*Y_MAX instances of a pe module. In pe.v, I want to initialize a memory generated specifically for that instance. For example, at x=0,y=1: "pe_memory_x0_y0.dat". This is what my top-level module looks like: genvar x, y; generate for (y = 0; y < Y_MAX; y = y + 1) begin : ys for (x = 0; x < X_MAX; x = x + 1) begin : xs pe #( .X_MAX(X_MAX), .Y_MAX(Y_MAX), .X(x), .Y(y) ) pe_inst( .clk(clk), ... ); Inside pe.v, things like $display("Loading pe memory at (%0d,%0d)", X, Y);

问题 In top.v, I generate X_MAX*Y_MAX instances of a pe module. In pe.v, I want to initialize a memory generated specifically for that instance. For example, at x=0,y=1: "pe_memory_x0_y0.dat". This is what my top-level module looks like: genvar x, y; generate for (y = 0; y < Y_MAX; y = y + 1) begin : ys for (x = 0; x < X_MAX; x = x + 1) begin : xs pe #( .X_MAX(X_MAX), .Y_MAX(Y_MAX), .X(x), .Y(y) ) pe_inst( .clk(clk), ... ); Inside pe.v, things like $display("Loading pe memory at (%0d,%0d)", X, Y);