问题
I'm using Xilinx ISE and generated a memory using the CORE Generator & Architecture Wizard.
The problem is that it created a write enable signal (wea) as a STD_LOGIC_VECTOR(0 downto 0) and that results in a type mismatch:
Line ###: Type error near encnt ; current type std_logic; expected type std_logic_vector
How can I cast encnt, which is std_logic, to a one bit std_logic_vector?
(ISE doesn't allow me to change wea from the file of memory.)
回答1:
This is a pretty common scenario with these IP blocks. You can easily associate your std_logic signal like this:
wea(0) => encnt,
Instead of associating wea as a whole, you are just associating that one element (0). As wea only has one element, this assigns the whole vector.
来源：https://stackoverflow.com/questions/49851974/connecting-a-std-logic-to-a-one-bit-std-logic-vector