xilinx-ise

问题 We are developing a system with a custom processor, Microblaze and some peripherals in VC709 FPGA using Xilinx Vivado. We are using two 'PCIe : BARs' in 'AXI Bridge for PCI express'. Initially the command 'lspci -vv' used to show memory regions in the Ubuntu teminal. $ lspci -vv 0a:00.0 Memory controller: Xilinx Corporation Device 7038 | 0a:00.0 Memory controller: Xilinx Corporation Device 7018 Subsystem: Xilinx Corporation Device 0007 | Subsystem: Xilinx Corporation Device 0008 Physical Slot

问题 We are developing a system with a custom processor, Microblaze and some peripherals in VC709 FPGA using Xilinx Vivado. We are using two 'PCIe : BARs' in 'AXI Bridge for PCI express'. Initially the command 'lspci -vv' used to show memory regions in the Ubuntu teminal. $ lspci -vv 0a:00.0 Memory controller: Xilinx Corporation Device 7038 | 0a:00.0 Memory controller: Xilinx Corporation Device 7018 Subsystem: Xilinx Corporation Device 0007 | Subsystem: Xilinx Corporation Device 0008 Physical Slot

问题 I'm working on a stopwatch project in VHDL but I don't know how to make the CLK square waveform of the counter? Please help. Here is my code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_unsigned.ALL; entity Circuit is Port ( CLK : in STD_LOGIC := '0'; CLR : in STD_LOGIC; Q : out STD_LOGIC_VECTOR (5 downto 0)); end Circuit; architecture Behavioral of Circuit is signal s: STD_LOGIC_VECTOR := "000000"; begin process (CLK, CLR) begin if rising_edge(CLK) then if CLR = '1' OR s =

问题 I want to get an accurate power report that contains real dynamic and static power consumption. I'm working on Xilinx spartan3 board. My code has no errors but after selecting the "Generate Text Power Report" in ISE (Xilinx synthesis tool), always the power report shows that my design has no dynamic power consumption. (Why?) Power report : Dynamic = 0.00 Quiescent = 59.84 Total = 59.84 My code : LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY SRAM IS PORT( clk : IN std_logic; wr : IN std

问题 I create this code from this curcuit Image Here And this is Error image Image Here This curcuit is Quadruple Bus Transcievers with 3-state outputs Verilog Code module Q52QuadrupleBus3Stlate(GAB,GBA,A,B); inout [3:0] A,B; input GAB,GBA; reg winA,winB; assign B = (GAB==1&&GBA==0) ? winA : 4'hz; assign A = (GAB==0&&GBA==1) ? winB : 4'hz; always @ (GAB or GBA) begin winA <= A; winB <= B; end endmodule Test Bench `timescale 1ps / 1ps module Q52TestBench; reg GAB; reg GBA; // Bidirs wire [3:0] A;

问题 I'm thinking about writing a C function which basically passes an array/vector of real numbers to a VHDL implementation as an argument and the VHDL code does some computation using the array in a FPGA and returns the result back to the C function. So, my question - How do I go about writing a C function to call the VHDL implementation? Can anyone guide me in the right direction like a tutorial,API or anything? Any help will be appreciated. Thanks! :) 回答1: VHDL does not result in a run time

问题 I'm using Xilinx ISE and generated a memory using the CORE Generator & Architecture Wizard. The problem is that it created a write enable signal ( wea ) as a STD_LOGIC_VECTOR(0 downto 0) and that results in a type mismatch: Line ###: Type error near encnt ; current type std_logic; expected type std_logic_vector How can I cast encnt , which is std_logic, to a one bit std_logic_vector? (ISE doesn't allow me to change wea from the file of memory.) 回答1: This is a pretty common scenario with these

问题 I am learning VHDL by reading books online (Free Range VHDL), and imlementing the examples on my Nexsys2 via Xilinx ISE Webpack 14.7. I am re-reading the Free Range VHDL text and am currently in the chapter discussing processes. I have a solid understanding of what a process is, and how it works, but I implemented an example and I do not understand the results. I implemented an 8 to 1 mux using the following code. library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity mux81 is port( d_in : in std

问题 code of booth multiplier is :- module ni(prod, a, b, busy, mc, mp, clk, start); output [15:0] prod; output [7:0] a, b; output busy; input [7:0] mc, mp; input clk, start; reg [7:0] A, Q, M; reg Q_1; reg [3:0] count; wire [7:0] sum, difference; always @(posedge clk) begin if (start) begin A <= 8'b0; M <= mc; Q <= mp; Q_1 <= 1'b0; count <= 4'b0; end else begin case ({Q[0], Q_1}) 2'b0_1 : {A, Q, Q_1} <= {sum[7], sum, Q}; 2'b1_0 : {A, Q, Q_1} <= {difference[7], difference, Q}; default: {A, Q, Q_1}

问题 I have the Xilinx Spartan6 and next VHDL code: library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity Switches_Leds is Port (switch_0: in STD_LOGIC; LED_0 : out STD_LOGIC); end Switches_Leds; architecture Behavioral of Switches_Leds is begin LED_0 <= switch_0; end; Here is my User constraint file: NET "switch_0" LOC = C3; NET "LED_0" LOC = P4; My question is: Why the led is always is turned on, but it goes off if I click on button ? I explain: I program my fpga - the led