Is $readmem synthesizable in Verilog?

问题

I am trying to implement a microcontroller on an FPGA, and I need to give it a ROM for its program. If I use $readmemb, will that be correctly synthesized to a ROM? If not, what is the standard way to do this?

回答1:

I would amend George's answer to say that it depends on the synthesis tool whether or not $readmemb is synthesizable.

Altera's Recommended HDL Coding Styles guide includes example 10-31 (page 10-38), which demonstrates a ROM inferred from $readmemb (reproduced below):

module dual_port_rom (
   input [(addr_width-1):0] addr_a, addr_b,
   input clk, 
   output reg [(data_width-1):0] q_a, q_b
);
   parameter data_width = 8;
   parameter addr_width = 8;
   reg [data_width-1:0] rom[2**addr_width-1:0];
   initial // Read the memory contents in the file
           // dual_port_rom_init.txt. 
   begin
      $readmemb("dual_port_rom_init.txt", rom);
   end
   always @ (posedge clk)
   begin
      q_a <= rom[addr_a];
      q_b <= rom[addr_b];
   end
endmodule

Similarly, Xilinx's XST User Guide states that:

The $readmemb and $readmemh system tasks can be used to initialize block memories. For more information, see:

Initializing RAM From an External File Coding Examples

Use $readmemb for binary and $readmemh for hexadecimal representation. To avoid the possible difference between XST and simulator behavior, Xilinx® recommends that you use index parameters in these system tasks. See the following coding example.

$readmemb("rams_20c.data",ram, 0, 7);

来源：https://stackoverflow.com/questions/4321067/is-readmem-synthesizable-in-verilog