hdl

Is it possible to instantiate a module conditionally in verliog ? example : if (en==1) then module1 instantiation else module2 instantiation From IEEE Std 1364-2001 : 12.1.3.3 generate-conditional A generate-conditional is an if-else-if generate construct that permits modules, user defined primitives, Verilog gate primitives, continuous assignments, initial blocks and always blocks to be conditionally instantiated into another module based on an expression that is deterministic at the time the design is elaborated. example given in LRM : module multiplier(a,b,product); parameter a_width = 8, b

What best practices should be observed when implementing HDL code? What are the commonalities and differences when compared to more common software development fields? The best book on this topic is Reuse Methodology Manual . It covers both VHDL and Verilog. And in particular some issues that don't have an exact match in software: No latches Be careful with resets Check your internal and external timing Use only synthesizable code Register your outputs of all modules Be careful with blocking vs. non-blocking assignments Be careful with sensitive lists for combinatorial logic (or use @(*) in

I've been stuck at this problem for some hours now, and it seems I can't find the solution by searching i.e. didn't find anything here or on Google. Here's my piece of code: LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.numeric_std; USE work.arrays.ALL; ENTITY parallel IS PORT (clk:IN std_logic; text:IN INT_ARRAY(119 DOWNTO 0); result:OUT INT_MATRIX_2D); END parallel; ARCHITECTURE arch OF parallel IS COMPONENT unit_comparator IS PORT (letter:IN integer; difference:OUT integer); END COMPONENT; SIGNAL temp: INT_MATRIX_2D := (others => (others => 0)); SIGNAL temp_differences: INT_ARRAY(119

Where Can I find algorithm details for holistic word recognition? I need to build a simple OCR system in hardware (FPGAs actually), and the scientific journals seems so abstract? Are there any open source (open core) codes for holistic word recognition? Thanks For an algorithm that is quite suitable for FPGA implementation (embarrassingly parallel) you might look at: http://en.wikipedia.org/wiki/Cross-correlation It is fast, and easily implemented. The only thing is: it recognizes a shape (in your case some text) DEPENDENT of the rotation and size / stretch / skew etc. But if that isn't a

I am trying to know the number of ones in a 4-bit binary number in verilog but no output happens. I've tried several approaches this is the one I think should work but it doesn't. module ones(one,in); input [3:0]in; output [1:0]one; assign one = 2'b00; assign one = one+in[3]+in[2]+in[1]+in[0] ; endmodule First, you can't assign the variable twice. Second, your range is off, 2 bits can only go from 0 to 3. You need a 3 bit output to count up to 4. This is more like what you need: module ones( output wire [2:0] one, input wire [3:0] in ); assign one = in[3]+in[2]+in[1]+in[0] ; endmodule toolic

What is the difference between: if (dataoutput[7:0] == 8'bx) begin and if (dataoutput[7:0] === 8'bx) begin After executing dataoutput = 52'bx , the second gives 1, but the first gives 0. Why? (0 or 1 is the comparison result.) Some data types in Verilog, such as reg , are 4-state. This means that each bit can be one of 4 values: 0,1,x,z. With the "case equality" operator, === , x's are compared, and the result is 1. With == , the result of the comparison is not 0, as you stated; rather, the result is x, according to the IEEE Std (1800-2009), section 11.4.5 "Equality operators": For the logical

I'm trying to create a multi-stage comparator in verilog and I can't figure out how to increment multiple genvars in a single generate loop. I'm trying the following: genvar i,j; //Level 1 generate j=0; for (i=0;i<128;i=i+1) begin: level1Comp assign ci1[i] = minw(tc[j],tc[j+1]); j = j+2; end endgenerate And getting the following error: Error-[SE] Syntax error Following verilog source has syntax error : "encoder.v", 322: token is '=' j=0; Anyone know how to increment multiple genvars in the same generate statement? Or at least get equivalent functionality? Assuming that ci1 has half the depth