digital-logic | 易学教程

Verilog Subtraction and addition

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问题 I am attempting to program an addition and subtraction program in Verilog. Problem is Implementation and testing in Verilog of a module that performs Addition or Subtraction, then a Mux chooses between letting go through the result of one or the other, and then Decode the selected result from binary into a 7-segment Display format. Verilog Module will have 3 inputs: two 4-bit inputs named A and B, and a select input S. Your circuit should add the two numbers and should also subtract B from A

Implementing a 2n-bit comparator using cascaded 2-bit comparators

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问题 So far I have this code for a 2-bit comparator. module twobitcomparator(xgtyin,xety,xltyin,x1,x0,y1,y0,xgty,xety,xlty); //I/O output xgty, xety, xlty; //xgty - x>y, xlty - x<y, xety - x=y input x1, x0, y1, y0, xgtyin, xetyin, xltyin; //specify circuit behavior assign r = (xgyin); assign s = (xlyin); assign t = (xetyin);//not sure if I need an xetyin assign a = (x1&~y1); assign b = (x1&x0&~y0); assign c = (x0&~y1&~y0); assign xgty = (a|b|c|r);//X>Y assign d = (~x0&~y0); assign e = (x0&y0);

Verilog error: Range must be bounded by constant expressions

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问题 I'm new to verilog and I am doing a project for my class. So here is my code: wire [n-1:0] subcounter_of_counter; reg [n-1:0] mask,free; //subcounter_of_counter: dinei ena vector apo poious subcounter apoteleitai o counter(id) always @(*) begin //command or id or mask or free or subcounter_of_counter if (command==increment) begin for (int i = 0; i < n; i=i+1)begin if (i<id) begin subcounter_of_counter[i]=1'b0; end else if (i==id) begin subcounter_of_counter[i]=1'b1; end else begin if( (|mask

Structure of VHDL code for barrel shifter with behavior architecture

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问题 I am trying to build a 16 bit barrel shifter with left and right shift capabilities. I am having some issues with how to structure the code so that it will do what I think I want to do. I have an opcode input that decides on the direction, an input vector to be shifted, an output vector, and a position vector with 4 bits. I am using the position vector to set a shift 'level' in a way. I want to check position(0) and if it is set to 1, shift one position. And then check position(1) and shift 2

Chisel runtime error in test harness

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问题 This Chisel code works ok: chiselMainTest(Array[String]("--backend", "c", "--genHarness"), () => Module( new Cache(nways = 16, nsets = 32) )){c => new CacheTests(c)} However this one - a small variation - produces run-time error: val cache_inst = new Cache(nways = 16, nsets = 32) chiselMainTest(Array[String]("--backend", "c", "--genHarness"), () => Module(cache_inst)){c => new CacheTests(c)} [error] (run-main) java.util.NoSuchElementException: head of empty list java.util

not a valid l-value - verilog compiler error

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问题 module fronter ( arc, length, clinic ) ; input [7:0] arc; output reg [7:0] length ; input [1:0] clinic; input en0, en1, en2, en3; // 11 // clock generator is here g_cal A( en0) ; g_cal B( en1) ; g_cal C( en2) ; g_cal D( en3) ; always @( negedge arc, posedge clk ) case ( clinic ) 2'b00 : { en3, en2, en1, en0 } = 4'b0001; // 23 2'b01 : { en3, en2, en1, en0 } = 4'b0010; // 24 2'b10 : { en3, en2, en1, en0 } = 4'b0100; // 25 2'b11 : { en3, en2, en1, en0 } = 4'b1000; // 26 default : { en3, en2, en1

How would you handle a special case in this digital logic system?

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问题 I posted this digital logic diagram as an answer to another stackoverflow question. It describes a logic system which will be coded in Verilog or VHDL and eventually implemented in an FPGA. alt text http://img145.imageshack.us/img145/5125/bitshifterlogicdiagramkn7.jpg The numbered boxes in the diagram represent bits in a field. Each field has K bits, and the bits for current and mask will be provided by a computer system (using a latched register or equivalent). The bits in next will be read

Why were bitwise operations slightly faster than addition/subtraction operations on older microprocessors?

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I came across this excerpt today: On most older microprocessors, bitwise operations are slightly faster than addition and subtraction operations and usually significantly faster than multiplication and division operations. On modern architectures, this is not the case: bitwise operations are generally the same speed as addition (though still faster than multiplication). I'm curious about why bitwise operations were slightly faster than addition/subtraction operations on older microprocessors. All I can think of that would cause the latency is that the circuits to implement addition/subtraction

Why were bitwise operations slightly faster than addition/subtraction operations on older microprocessors?

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问题 I came across this excerpt today: On most older microprocessors, bitwise operations are slightly faster than addition and subtraction operations and usually significantly faster than multiplication and division operations. On modern architectures, this is not the case: bitwise operations are generally the same speed as addition (though still faster than multiplication). I'm curious about why bitwise operations were slightly faster than addition/subtraction operations on older microprocessors.