How would you handle a special case in this digital logic system?

问题

I posted this digital logic diagram as an answer to another stackoverflow question. It describes a logic system which will be coded in Verilog or VHDL and eventually implemented in an FPGA.

alt text http://img145.imageshack.us/img145/5125/bitshifterlogicdiagramkn7.jpg

The numbered boxes in the diagram represent bits in a field. Each field has K bits, and the bits for current and mask will be provided by a computer system (using a latched register or equivalent). The bits in next will be read back into that same computer system.

The solution that I posted works as long as there is at least one bit set in the mask field, and there is exactly one bit set in the current bit field. The idea is that the next bit field will become the current bit field after the computer system has performed some task (a scheduling operation, in the original question).

So, my question is this: How would you modify this system so that it properly handles the special case where the current bit field is all zero (no bits set)? As it stands, if all bits in current are zero, the output will also be zero, no matter what the bits in mask are set to.

Ideally, if current is all zeroes, the lowest set bit in mask should be set in next. The system should also still remain scalable to any number of bits (K) without having to add exponentially more logic gates. The spirit of the original question was to come up with a solution that would be straightforward to implement for any number of bits.

回答1:

For me, I would tell the user of the FPGA that they must have one of the bits set to 1 on entry.

However, if that's not your preferred solution, what's wrong with the idea of pre-feeding all the Current inputs initially into a big NOR gate (so that the output is true only when all inputs are false). All Current lines also continue through to their AND gates with the exception that Current[1] is OR'ed with the output of our NOR gate before entering it's AND gate

That way, Current[1] would be true entering the AND gate, if all Currents are false.

Keep in mind that I understand boolean algebra but I've never worked on raw hardware - I'm guessing you'll need to buffer all the input signals into the AND gates to ensure correct timing but i suspect you'll know that better than I.

The following diagram is left in in case SO fixes its code/pre blocks - the latest SO update seems to have stuffed them up (leaving them proportional, not fixed-width, font). Anyway, eJames' graphical diagram is better.

Here's my diagram, slightly less elegant than yours :-):

               +-------------------+
               |                   |
               |     +----         |
Current[1]-----+------\   \        |
                       |NOR|o--+   |
Current[2-k]---+------/   /    |   |
               |     +----     |   |
               |              +\   /+
               |              | \_/ |
             +---+            |  OR |
              \ /Buffer        \   /
               +                ---
               |                 |
             +---+             +---+
             |2-k|             | 1 |    <- These signals feed 
             +---+             +---+       into your AND gates.

来源：https://stackoverflow.com/questions/486473/how-would-you-handle-a-special-case-in-this-digital-logic-system

标签

hardware

boolean-logic

digital-logic