arm

ARM assembly: auto-increment register on store

北慕城南 提交于 2020-08-21 06:46:10
问题 Is it possible to auto-increment the base address of a register on a STR with a [Rn]! ? I've peered through the documentation but haven't been able to find a definitive answer, mainly because the command syntax is presented for both LDR and STR - in theory it should work for both, but I couldn't find any examples of auto-incrementing on a store (the loading works ok). I've made a small program which stores two numbers in a vector. When it's done the contents of out should be {1, 2} but the

How to generate a .so file from multiple source files

丶灬走出姿态 提交于 2020-08-05 09:37:53
问题 I have been trying from the past few days for generating a shared library. I have header files, source files and asm files as well. I have tried to follow quiet a number of similar questions but I was not able to locate one that specifies the steps needed to generate a .so file from multiple source, header and asm files. I have been facing many issues for generating the .so file. If someone could help me with the step by step procedure for generating a .so file, I would be very grateful. Also

How to generate a .so file from multiple source files

断了今生、忘了曾经 提交于 2020-08-05 09:35:28
问题 I have been trying from the past few days for generating a shared library. I have header files, source files and asm files as well. I have tried to follow quiet a number of similar questions but I was not able to locate one that specifies the steps needed to generate a .so file from multiple source, header and asm files. I have been facing many issues for generating the .so file. If someone could help me with the step by step procedure for generating a .so file, I would be very grateful. Also

How to generate a .so file from multiple source files

北城余情 提交于 2020-08-05 09:34:21
问题 I have been trying from the past few days for generating a shared library. I have header files, source files and asm files as well. I have tried to follow quiet a number of similar questions but I was not able to locate one that specifies the steps needed to generate a .so file from multiple source, header and asm files. I have been facing many issues for generating the .so file. If someone could help me with the step by step procedure for generating a .so file, I would be very grateful. Also

How to check the existence of NEON on arm?

喜夏-厌秋 提交于 2020-08-01 06:20:26
问题 How to determine whether NEON engine exists on given ARM processor? Any status/flag register can be queried for such purpose? 回答1: I believe unixsmurf's answer is about as good as you'll get if using an OS with privileged kernel. For general purpose feature detection, it seems ARM has made it a requirement to get this from the OS, and so you must use an OS API to get it. On Android NDK use #include <cpu-features.h> with (android_getCpuFamily() == ANDROID_CPU_FAMILY_ARM) && (android

How to check the existence of NEON on arm?

旧城冷巷雨未停 提交于 2020-08-01 06:20:26
问题 How to determine whether NEON engine exists on given ARM processor? Any status/flag register can be queried for such purpose? 回答1: I believe unixsmurf's answer is about as good as you'll get if using an OS with privileged kernel. For general purpose feature detection, it seems ARM has made it a requirement to get this from the OS, and so you must use an OS API to get it. On Android NDK use #include <cpu-features.h> with (android_getCpuFamily() == ANDROID_CPU_FAMILY_ARM) && (android

ARM, VFP, floating-point, lazy context switching

℡╲_俬逩灬. 提交于 2020-07-21 06:37:04
问题 I am writing an operating system for an ARM processor (Cortex-A9). I am trying to implement lazy context switching of the floating-point registers. The idea behind this is that the floating-point extension is initially disabled for a thread and so there is no need to save floating-point context on a task-switch. When a thread attempts to use a floating-point instruction, it triggers an exception. The operating system then enables floating-point extension and knows that floating-point context

ARM Cortex M4 SVC_Handler “UsageFault”

北城余情 提交于 2020-07-19 18:44:47
问题 I'm creating a context switch program for a personal mini ARM kernel project and the context switch program is written entirely in Assembly. The problem is when I make a SVC call (svc 0) I enter the SVC_Handler but when I try to execute the next instruction I then enter a different handler ("UsageFault_Handler"). The fault occurs before I can pop any of the registers in the SVC_Handler. Here's a register dump of my gdb screen (right after I enter SVC_Handler and encounter UsageFault_Handler):

ARM Cortex M4 SVC_Handler “UsageFault”

岁酱吖の 提交于 2020-07-19 18:44:13
问题 I'm creating a context switch program for a personal mini ARM kernel project and the context switch program is written entirely in Assembly. The problem is when I make a SVC call (svc 0) I enter the SVC_Handler but when I try to execute the next instruction I then enter a different handler ("UsageFault_Handler"). The fault occurs before I can pop any of the registers in the SVC_Handler. Here's a register dump of my gdb screen (right after I enter SVC_Handler and encounter UsageFault_Handler):

ARM Cortex M4 SVC_Handler “UsageFault”

孤者浪人 提交于 2020-07-19 18:43:05
问题 I'm creating a context switch program for a personal mini ARM kernel project and the context switch program is written entirely in Assembly. The problem is when I make a SVC call (svc 0) I enter the SVC_Handler but when I try to execute the next instruction I then enter a different handler ("UsageFault_Handler"). The fault occurs before I can pop any of the registers in the SVC_Handler. Here's a register dump of my gdb screen (right after I enter SVC_Handler and encounter UsageFault_Handler):