arm

Are writes on the PCIe bus atomic?

99封情书 提交于 2020-07-09 07:36:11
问题 I am a newbie to PCIe, so this might be a dumb question. This seems like fairly basic information to ask about PCIe interfaces, but I am having trouble finding the answer so I am guessing that I am missing some information which makes the answer obvious. I have a system in which I have an ARM processor (host) communicating to a Xilinx SoC via PCIe (device). The endpoint within the SoC is an ARM processor as well. The external ARM processor (host) is going to be writing to the register space

ARM single-copy atomicity

我的梦境 提交于 2020-06-26 04:11:25
问题 I am currently wading through the ARM architecture manual for the ARMv7 core. In chapter A3.5.3 about atomicity of memory accesses, it states: If a single-copy atomic load overlaps a single-copy atomic store and for any of the overlapping bytes the load returns the data written by the write inserted into the Coherence order of that byte by the single-copy atomic store then the load must return data from a point in the Coherence order no earlier than the writes inserted into the Coherence

GCC: How to disable heap usage entirely on an MCU?

早过忘川 提交于 2020-06-24 22:42:24
问题 I have an application that runs on an ARM Cortex-M based MCU and is written in C and C++. I use gcc and g++ to compile it and would like to completely disable any heap usage. In the MCU startup file the heap size is already set to 0. In addition to that, I would also like to disallow any accidental heap use in the code. In other words, I would like the linker (and/or the compiler) to give me an error when the malloc , calloc , free functions or the new , new[] , delete , delete[] operators

Scanf ARM Assembly

我与影子孤独终老i 提交于 2020-06-23 05:16:09
问题 I know there's a question here but I really don't understand what the OP did. I've used x86 assembly before and for that you'd do something like this: push dword int1 push dword fmtInput call scanf add esp, 12 ; value is now in int1 my guess for ARM is something like this ldr r0, fmtInput push r1 @ says this is too complex, tried `ldr r1` but that also failed saying that ldr needed more inputs bl scanf @ I'm assuming the value is now in r1 I'm sure I'm missing something simple but I'm really

STM32 Freezing periphirals when pausing the debugger

て烟熏妆下的殇ゞ 提交于 2020-06-14 08:35:12
问题 Debugger can stop execution of code in Cortex when it reaches a breakpoint or user pauses the execurion of code. But does debugger freeze other periphirals like DMA, UART and TIMERS when cortex stops execuring the code in pause state? 回答1: You can only hold time/r depend peripherals. I call the following code on entering the main function: DBGMCU->APB1FZ |= DBGMCU_APB1_FZ_DBG_TIM2_STOP | DBGMCU_APB1_FZ_DBG_TIM3_STOP | DBGMCU_APB1_FZ_DBG_TIM4_STOP | DBGMCU_APB1_FZ_DBG_TIM5_STOP); DBGMCU-

How to build kernel debug info as separate file?

浪子不回头ぞ 提交于 2020-05-28 07:48:50
问题 When we share custom built kernel, It is common to give without debug info. Similar to sudo apt-get install linux-image-$(uname -r)-dbgsym , I would like to create separate debug info file for custom built kernel. Here and here they explained generally. I request to share knowledge on creating separate debug info file for entire linux kernel. For sample program $ gcc -g calc.c $ ls -l total 16 -rwxrwxr-x 1 jeyaram jeyaram 8424 Apr 8 09:44 a.out -rw-rw-r-- 1 jeyaram jeyaram 246 Apr 8 09:32

Determining the library which causes “Illegal instruction” on a Pi Zero W (armv6), and fixing the build

孤人 提交于 2020-05-28 06:53:22
问题 I understand that a lot of compilation issues on the Pi Zeros are due to the fact that they use armv6, whereas the newer Raspberry Pi's like the 3 A+ and B+ use armv7. However, I do not understand how to find the offending library in an application that is causing the issue, and if there is perhaps a simple fix for the problem. Background: I am trying to port an application from a Linux Desktop environment to the Pi Zero (running armv6). I successfully ported it to the Pi 3 B and B+. That is,

ARM/neon memcpy optimized for *uncached* memory?

ⅰ亾dé卋堺 提交于 2020-05-25 05:29:09
问题 I'm using a Xilinx Zynq 7000 ARM-based SoC. I'm struggling with DMA buffers (Need help mapping pre-reserved **cacheable** DMA buffer on Xilinx/ARM SoC (Zynq 7000)), so one thing I pursued was faster memcpy. I've been looking at writing a faster memcpy for ARM using Neon instructions and inline asm. Whatever glibc has, it's terrible, especially if we're copying from an ucached DMA buffer. I've put together my own copy function from various sources, including: Fast ARM NEON memcpy arm Inline

Executing programs stored in external SPI flash memory on an ARM processor

做~自己de王妃 提交于 2020-05-24 21:03:13
问题 I have an ARM processor that is able to interface with an external flash memory chip. Written to the chip are programs compiled for the ARM architecture ready to be executed. What I need to know how to do is get this data from the external flash onto the ARM processor for execution. Can I run some sort of copy routine ahead-of-time where the data is copied into executable memory space? I suppose I could, but the ARM processor is running an operating system and I don't have a ton of space left

Executing programs stored in external SPI flash memory on an ARM processor

回眸只為那壹抹淺笑 提交于 2020-05-24 20:59:09
问题 I have an ARM processor that is able to interface with an external flash memory chip. Written to the chip are programs compiled for the ARM architecture ready to be executed. What I need to know how to do is get this data from the external flash onto the ARM processor for execution. Can I run some sort of copy routine ahead-of-time where the data is copied into executable memory space? I suppose I could, but the ARM processor is running an operating system and I don't have a ton of space left