Using FOR loop in VHDL with a variable

Question

Is there any possible way to create a for loop in the form:

for i in 0 to some_var loop
    // blah,blah
end loop;

If not, is there any alternative way to create the same loop? Since While loops allows to use variable as the limit, but they are not synthesizeable in my project.

Thanks in Advance,

Bojan Matovski

Answer 1

The variable works just fine for testbench applications.

For synthesis you can get the same effect by using a static range and an exit condition. Set the range to be the maximum you will need.

for i in 0 to MAX_VALUE loop
  exit when i = some_var ;
  // blah,blah
end loop;

If your synthesis tool chokes on this, file a bug report. Both 1076.6-1999 and 1076.6-2004 (VHDL RTL Synthesis Standards) indicate that exit conditions are supported for "for" loops with a static range. You may find support issues with respect to using a loop label (1076.6-1999) indicates it is not supported.

If you find a bug (or lack of support) and do not report it, your vendor will think it is a feature you don't care about, and hence, will not invest in changing their tool.

Answer 2

Only loop parameters with static range are synthesizable.

You can implement a FSM(finite state machine) if some_var has a discrete range. Then write a specific loop for each state.