VHDL-2008 external names: reference verilog net?

问题

Is it possible to use VHDL-2008 hierarchical references / external names to reference Verilog nets? Questa Sim (10.6c) stops the simulation with this error message:

vsim-8509: The object class "SIGNAL" of "dut_i.my_net" is different from the class "net" of the denoted object.

Here's the VHDL code that fails:

alias my_alias is << signal dut_i.my_net : std_logic >>;

回答1:

According to the Questa User Manual:

Questa SIM supports the IEEE 1076-2008 standard “external name” syntax that allows you to make hierarchical references from VHDL to VHDL. Currently, these references can cross Verilog boundaries, but they must begin and end in VHDL.

Thus, the answer is no.

Questa does provide a set of Signal Spy procedures to access your Verilog signals via string names. You must also turn on optimization visability to access these signals since the strings are not parsed until run-time.

来源：https://stackoverflow.com/questions/54213587/vhdl-2008-external-names-reference-verilog-net