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VHDL-2008 external names: reference verilog net?

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问题 Is it possible to use VHDL-2008 hierarchical references / external names to reference Verilog nets? Questa Sim (10.6c) stops the simulation with this error message: vsim-8509: The object class "SIGNAL" of "dut_i.my_net" is different from the class "net" of the denoted object. Here's the VHDL code that fails: alias my_alias is << signal dut_i.my_net : std_logic >>; 回答1: According to the Questa User Manual: Questa SIM supports the IEEE 1076-2008 standard “external name” syntax that allows you

call questa sim commands from SystemVerilog test bench

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问题 I want to call questa sim commands like add wave ,add list, write list from my SystemVerilog test bench task add_files_to_list(); add wave -position insertpoint sim:/top/clk add list sim:/top/clk write list -window .main_pane.list.interior.cs.body /home/simulation/top/example.lst endtask but the above doesn't work when i do from system verilog, i have to do i manually from tool. is there any way to do it. or can i call a tcl script from my system verilog code. Thanks 回答1: mti_fli::mti_Cmd(

Why should an HDL simulation (from source code) have access to the simulator's API?

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问题 This is a question inspired by this question and answer pair: call questa sim commands from SystemVerilog test bench The questions asks how Verilog code could control the executing simulator (QuestaSim). I saw similar questions and approaches for VHDL, too. So my question is: Why should a simulation (slave) have power of its simulator (master)? What are typical use cases? Further reading: call questa sim commands from SystemVerilog test bench VerTcl - A Tcl interpreter implemented in VHDL 回答1

How to write a makefile where the compiled object files are in a different directory with a different name?

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问题 So I'm trying to write a Makefile to use with QuestaSim and systemverilog files. If you don't know what that is (and most people won't) then don't worry, it's not that relevant to my problem. I have a project director containing: src/ work/ Makefile the src/ directory contains several directories which each contain source files. the work/ directory doesn't initially exist, and is created by the makefile. when I call my "compiler" which is called vlog, on a .sv file a directory gets created in

TCL wildcard/glob usage within file name

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I have code that is like this: ... proc myProc {first last} { for { set i $first } { $i <= $last } { incr i } { set i_cur "PlainText$i" <command> [glob ./../myDir/${i_cur}*] } } When I run this, any file that has nothing after the number will run fine. But if there is something after the number then it doesn't. For example, I have the valid files named PlainText0.txt , PlainText00.txt , and PlainText1_Plaintext.txt . The first two work and PlainText1_Plaintext.txt doesn't. Basically, I do not think I am using a glob/wildcard correctly, but don't know how. The usual issues with this sort of

TCL wildcard/glob usage within file name

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问题 I have code that is like this: ... proc myProc {first last} { for { set i $first } { $i <= $last } { incr i } { set i_cur "PlainText$i" <command> [glob ./../myDir/${i_cur}*] } } When I run this, any file that has nothing after the number will run fine. But if there is something after the number then it doesn't. For example, I have the valid files named PlainText0.txt , PlainText00.txt , and PlainText1_Plaintext.txt . The first two work and PlainText1_Plaintext.txt doesn't. Basically, I do not