sensitivity list VHDL process

问题

I'm trying to learn VHDL using Peter Ashenden's book 'The Designer's Guide to VHDL', but can't seem to shake the feeling that I have missed a fundamental item related to sensitivity lists.

for example a question is "Write a model that represents a simple ALU with integer inputs and output, and a function select input of type bit. if the function select is '0', the ALU output should be the sum of the inputs otherwise the output should be the difference of the inputs."

My solution to this is

entity ALU is

  port (
    a : in  integer;                    -- A port
    b : in  integer;                    -- B port
    sel : in bit;                       -- Fun select
    z  : out integer);                  -- result
end entity ALU;

architecture behav of ALU is

begin  -- architecture behav
  alu_proc: process is
  variable result : integer := 0;
  begin  -- process alu_proc
    wait on sel;
    if sel = '0' then
      result := a + b;
    else
      result := a - b;
    end if;
    z <= result;
  end process alu_proc;
end architecture behav;

with the test bench

entity alu_test is
end entity alu_test;

architecture alu_tb of alu_test is
signal a, b, z : integer;
signal sel : bit;
begin  -- architecture alu_tb

  dut: entity work.alu(behav)
    port map (a, b, sel, z);

  test_proc: process is
  begin  -- process test_proc

  a <= 5; b <= 5; wait for 5 ns; sel <= '1'; wait for 5 ns;
  assert z = 0;

  a <= 10; b <= 5; wait for 5 ns; sel <= '0'; wait for 5 ns;
  assert z = 15;

  wait;
  end process test_proc;
end architecture alu_tb;

my issue has to do with the sensitivity list in the process. Since it is sensitive to changes of the select bit I must do the functions sequentially, first an subtraction, then an addition then a subtraction again in the test bench. In the question I get the feeling that you should be able to do several additions sequentially, no subtraction between. Of course I can add an enable signal and have the process be sensitive to that but I think that should be told in the questions then. Am I missing something in the language or is my solution "correct"?

回答1:

The problem with the ALU process is that the wait on sel; does not include a and b, thus the process does not wake up and the output is not recalculated at changes to these inputs. One way to fix this is to add a and ´b´ to the wait statement, like:

wait on sel, a, b;

However, the common way to write this for processes is with a sensitivity list, which is a list of signals after the process keyword, thus not with the wait statement.

Ashendens book 3rd edition page 68 describes that a sensitivity list:

The process statement includes a sensitivity list after the keyword process. This is a list of signals to which the process is sensitive. When any of these signals changes value, the process resumes and executes the sequential statements. After it has executed the last statement, the process suspends again.

The use of sensitivity list as equivalent to wait statement is also described in Ashendens book on page 152.

If the process is rewritten to use a sensitivity list, it will be:

alu_proc: process (sel, a, b) is
begin  -- process alu_proc
  if sel = '0' then
    z <= a + b;
  else
    z <= a - b;
  end if;
end process alu_proc;

Note that I removed the result variable, since the z output can just as well be assigned directly in this case.

The above will recalculate z when any of the values used in the calculation changes, since all the arguments for calculating z are included in the sensitivity list. The risk of doing such continuous calculations in this way, is that if one or more of the arguments are forgotten in the sensitivity list, a new value for z is not recalculated if the forgotten argument changes.

VHDL-2008 allows automatic inclusion of all signals and ports in the sensitivity list if all is used like:

alu_proc: process (all) is

A final comment, then for a simple process doing asynchronous calculation, like for the shown ALU, it is possible to do without a process, if the generation of z is written like:

z <= (a + b) when (sel = '0') else (a - b);

Using a concurrent assignment, like the above, make it possible to skip the sensitivity list, and thus the risk of forgetting one of the signals or ports that are part of the calculation.

来源：https://stackoverflow.com/questions/27763926/sensitivity-list-vhdl-process

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vhdl