How to keep all variable name In chisel when generate Verilog code

问题

The Register name in chisel can be definitly found in verilog ,.
but Wire name sometimes ellipsis in verilog code.

for example , I cant find sjwr ,sjwaddr name in verilog .

  val sjwr = Wire(Bool()) 
  val sjwaddr = Wire(UInt(jcnt.getWidth.W))
  sjwr    := jcnt_rdy 
  sjwaddr := jcnt
  when (sjwr) { sjBuf(sjwaddr) := sjxv }

How can i keep all variable name in chisel when we generate verilog code .
it's important for wave debug.

回答1:

Thank you for your interest in Chisel!

There are several reasons why a name may be disappearing.

Constant Propagation

For many reasons, including interoperability with existing CAD tools, performance, and Verilog debug-ability, Chisel (actually the FIRRTL compiler underneath Chisel) will propagate constants and direct wire connections. For example:

class MyModule extends Module {
  val io = IO(new Bundle {
    val in = Input(UInt(8.W))
    val out = Output(UInt(8.W))
  })
  val wire = Wire(UInt(8.W))
  wire := io.in
  io.out := wire
}

In the above code, wire will be removed because it is simply connected to io.in, the Verilog will just show:

assign io_out = io_in;

Inability to name

Chisel Modules are implemented as Scala Classes. Due to implementation reasons, by default Chisel can only name "top-level" vals in the body of the Module, for example:

class MyModule extends Module {
  val io = IO(new Bundle {
    val in = Input(UInt(8.W))
    val in2 = Input(UInt(8.W))
    val out = Output(UInt(8.W))
  })
  val sum = io.in + io.in2 // this is a top-level val, will be named

  // A method, we can call to help generate code:
  def inc(x: UInt): UInt = {
    val incremented = x + 1.U // We cannot name this, it's inside a method
    incremented
  }

  io.out := inc(sum)
}

suggestName

You can manually name any signal by calling .suggestName("name") on it, eg.

  def inc(x: UInt): UInt = {
    val incremented = x + 1.U // We cannot name this, it's inside a method
    incremented.suggestName("incremented") // Now it is named!
  }

Enter @chiselName

We can fix the above issue with an experimental feature called @chiselName like so:

import chisel3.experimental.chiselName

@chiselName
class MyModule extends Module {
  val io = IO(new Bundle {
    val in = Input(UInt(8.W))
    val in2 = Input(UInt(8.W))
    val out = Output(UInt(8.W))
  })
  val sum = io.in + io.in2 // this is a top-level val, will be named

  // A method, we can call to help generate code:
  def inc(x: UInt): UInt = {
    val incremented = x + 1.U // We cannot name this, it's inside a method
    incremented
  }

  io.out := inc(sum)
}

@chiselName is an annotation that can be used on any class or object definition and will ensure vals like incremented can get named. @chiselName effectively rewrites your code to put .suggestName all over the place.

I hope this helps!

EDIT more info:

Disabling Optimizations

I don't think it's in a release yet (most recent being 3.1.7, this will be in 3.2.0), but we do have an option to disable all optimizations. You can change the "compiler" used from verilog to mverilog (for "minimum" Verilog, ie. no optimizations). This can be done with the command-line argument -X mverilog either in Chisel or FIRRTL.

Don't Touch

You can also use chisel3.dontTouch to mark a signal as something that shouldn't be deleted. This will prevent optimizations from removing the signal. For example:

import chisel3.dontTouch
class MyModule extends Module {
  val io = IO(new Bundle {
    val in = Input(UInt(8.W))
    val out = Output(UInt(8.W))
  })
  val wire = dontTouch(Wire(UInt(8.W)))
  wire := io.in
  io.out := wire

EDIT 2: I've updated for Chisel 3.2 where dontTouch moved from package chisel3.experimental to the regular chisel3 package

来源：https://stackoverflow.com/questions/55401525/how-to-keep-all-variable-name-in-chisel-when-generate-verilog-code

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Chisel