问题
What is the difference between the following 2 snippets of verilog code?
1)
always@(in)
out = #5 in;
AND
2)
always@(in)
out <= #5 in;
Considering no other lines are present in the always block, can there be any difference in output? question is in reference to slide 16 (see o5 and o6 outputs) http://www.sutherland-hdl.com/papers/1996-CUG-presentation_nonblocking_assigns.pdf
回答1:
out = #5 in; blocks the next operation for 5 time units. It will prevent the monitoring of the next @(in) until the the 5 time units have passed. If you add a $display statement just before and after the assignment you will see 5 time units has passed.
always @(in) begin
$display("enter @ %0t",$realtime);
out = #5 in;
$display("exit @ %0t",$realtime);
end
/*******************
* Example output:
* enter @ time 10
* exit @ time 15
*******************/
out <= #5 in; schedules the assignment of occur 5 time units in the future and allows the next operation to begin without waiting for assignment to complete.
always @(in) begin
$display("enter @ %0t",$realtime);
out <= #5 in;
$display("exit @ %0t",$realtime);
end
/*******************
* Example output:
* enter @ time 10
* exit @ time 10
*******************/
Working example at the EDA Playground: http://www.edaplayground.com/s/6/114
回答2:
They produce different output when in toggles before the #5 delay is up. The non-blocking assignment will always delay in by #5 regardless of how fast in toggles.
Examples on EDA Playground. Note the difference in sim output.
- Blocking assignment
- Non-Blocking assignment
来源：https://stackoverflow.com/questions/18455750/difference-between-blocking-and-non-blocking-statements-with-intra-assignment-de