inout with reg type in verilog

问题

I have used inout with c but for c to be on the LHS of procedural assignment, it needs to be a reg type variable. Can anyone help me out with this code?

module multiedgeclk(input clk ,[7:0] a,b,d, inout [7:0] c, output reg [7:0]f); 
always @(posedge clk)
c <= a + b;
always @(negedge clk)
f = c & d;
endmodule

回答1:

In verilog inout is the direction of the port. wire or reg is the type of the signal. If you want to drive a bi-directional port, it should be declare as inout wire or inout and drive it with enable signal Here is a example of bi-directional port.

module ABC( inout [7:0] c );
reg [7:0] c_out;
reg out_en;
assign c = out_en ? 8'hz : c_out; 
/* something here
... 
*/
endmodule

回答2:

An inout port cannot be procedurally assigned. There is nothing to indicate how long to hold that value on the port. This is the problem for any wire. But wires have a strength mechanism for multiple continuous drivers, highest strength wins. So you can use a continuous assignment to selectively drive a value or turn it off by driving a z value.

wire c; reg c_reg;

assign c = c_reg;

Now you can procedurally assign c_reg to a value or 8'bz

See my article for more info about wires and reg types.

来源：https://stackoverflow.com/questions/50821122/inout-with-reg-type-in-verilog