x86

问题 How do I create/handle simple bmp file filling it with one color only using intel 64 bit assembly and nasm assembler? 回答1: The steps that include such operation are: Create bmp file header with fixed values (explanation of specific fields below) Create buffer which contains enough space - three bytes per pixel (one color = red + green + blue) Open/create file Fill the buffer Write header to file Write buffer to file Close file Exit program Ad. 2: This is a bit more tricky - if the number of

问题 How do I create/handle simple bmp file filling it with one color only using intel 64 bit assembly and nasm assembler? 回答1: The steps that include such operation are: Create bmp file header with fixed values (explanation of specific fields below) Create buffer which contains enough space - three bytes per pixel (one color = red + green + blue) Open/create file Fill the buffer Write header to file Write buffer to file Close file Exit program Ad. 2: This is a bit more tricky - if the number of

问题 How do I create/handle simple bmp file filling it with one color only using intel 64 bit assembly and nasm assembler? 回答1: The steps that include such operation are: Create bmp file header with fixed values (explanation of specific fields below) Create buffer which contains enough space - three bytes per pixel (one color = red + green + blue) Open/create file Fill the buffer Write header to file Write buffer to file Close file Exit program Ad. 2: This is a bit more tricky - if the number of

问题 In gcc inline assembly examples found on the net, I see register names being referenced sometimes with a single % and other times with two (i.e. %% ). It's not clear when to use a single % and when to use %% . e.g. please see below example. /* Do b = a */ int a=10, b; asm ("movl %1, %%eax;\n" "movl %%eax, %0;" : "=r" (b) /* output */ : "r" (a) /* input */ : "%eax" /* clobbered register */ ); This example which uses %% prefix for EAX register compiles fine on my x86 machine (Linux RedHat 5.6

问题 In gcc inline assembly examples found on the net, I see register names being referenced sometimes with a single % and other times with two (i.e. %% ). It's not clear when to use a single % and when to use %% . e.g. please see below example. /* Do b = a */ int a=10, b; asm ("movl %1, %%eax;\n" "movl %%eax, %0;" : "=r" (b) /* output */ : "r" (a) /* input */ : "%eax" /* clobbered register */ ); This example which uses %% prefix for EAX register compiles fine on my x86 machine (Linux RedHat 5.6

问题 Trying to implement hardware interrupts on a test bootloader. Exceptions are working(thus found it is GPF). When trying to sti , a GPF is occured. Here is my main code: cli lgdt [gdt_desc] lidt [idt_desc] mov eax, cr0 or eax, 1 mov cr0, eax jmp 0x8:bit_32 bit_32: [bits 32] mov ax, 0x10 mov ds, ax mov es, ax mov fs, ax mov gs, ax mov ss, ax mov eax, 0x8000 mov esp, eax mov ebp, esp sti ; exception raised This is how my GDT looks like: start_gdt: null: dd 0x0 dd 0x0 code: dw 0xffff dw 0x0 db

问题 Trying to implement hardware interrupts on a test bootloader. Exceptions are working(thus found it is GPF). When trying to sti , a GPF is occured. Here is my main code: cli lgdt [gdt_desc] lidt [idt_desc] mov eax, cr0 or eax, 1 mov cr0, eax jmp 0x8:bit_32 bit_32: [bits 32] mov ax, 0x10 mov ds, ax mov es, ax mov fs, ax mov gs, ax mov ss, ax mov eax, 0x8000 mov esp, eax mov ebp, esp sti ; exception raised This is how my GDT looks like: start_gdt: null: dd 0x0 dd 0x0 code: dw 0xffff dw 0x0 db

问题 X86 guarantees a total order over all stores due to its TSO memory model. My question is if anyone has an idea how this is actually implemented. I have a good impression how all the 4 fences are implemented, so I can explain how local order is preserved. But the 4 fences will just give PO; it won't give you TSO (I know TSO allows older stores to jump in front of newer loads so only 3 out of 4 fences are needed). Total order over all memory actions over a single address is responsibility of

问题 Are there any other processor registers (e.g. flags) besides the architectural registers (eax, ebx,.) in x86 for which RAW dependencies need to be enforced by the scoreboard in pipelined processors? 回答1: Literally every register guarantees that if you write it, later instructions will read the new value. x86 is defined in terms of serial execution; pipelining and out-of-order exec need to preserve that illusion for everything , including segment registers, FP rounding modes, control and debug

问题 I have the inline assembly code: #define read_msr(index, buf) asm volatile ("rdmsr" : "=d"(buf[1]), "=a"(buf[0]) : "c"(index)) The code using this macro: u32 buf[2]; read_msr(0x173, buf); I found the disassembly is(using gnu toolchain): mov eax,0x173 mov ecx,eax rdmsr mov DWORD PTR [rbp-0xc],edx mov DWORD PTR [rbp-0x10],eax The question is that 0x173 is less than 0xffff, why gcc does not use "mov cx, 0x173"? Will the gcc analysis the following instruction "rdmsr"? Will the gcc always know the