x86

问题 I was trying to divide (Unsigned) 8A32F4D5 by C9A5 using emu8086 tool. I expected the quotient to be AF73H and the remainder be 94B6H . After writing the following code, I was getting correct quotient but the remainder became 0000h . Am I missing something? .MODEL SMALL .STACK 100H .DATA .CODE MAIN PROC ; initialize DS MOV AX,@DATA MOV DS,AX ; enter your code here MOV DX, 8A32H MOV AX, 0F4D5H MOV BX, 0C9A5H DIV BX ;exit to DOS MOV AX,4C00H INT 21H MAIN ENDP END MAIN The output in EMU8086: 回答1

问题 I was trying to divide (Unsigned) 8A32F4D5 by C9A5 using emu8086 tool. I expected the quotient to be AF73H and the remainder be 94B6H . After writing the following code, I was getting correct quotient but the remainder became 0000h . Am I missing something? .MODEL SMALL .STACK 100H .DATA .CODE MAIN PROC ; initialize DS MOV AX,@DATA MOV DS,AX ; enter your code here MOV DX, 8A32H MOV AX, 0F4D5H MOV BX, 0C9A5H DIV BX ;exit to DOS MOV AX,4C00H INT 21H MAIN ENDP END MAIN The output in EMU8086: 回答1

问题 I was trying to divide (Unsigned) 8A32F4D5 by C9A5 using emu8086 tool. I expected the quotient to be AF73H and the remainder be 94B6H . After writing the following code, I was getting correct quotient but the remainder became 0000h . Am I missing something? .MODEL SMALL .STACK 100H .DATA .CODE MAIN PROC ; initialize DS MOV AX,@DATA MOV DS,AX ; enter your code here MOV DX, 8A32H MOV AX, 0F4D5H MOV BX, 0C9A5H DIV BX ;exit to DOS MOV AX,4C00H INT 21H MAIN ENDP END MAIN The output in EMU8086: 回答1

问题 I have found out that both mul and imul can be used to multiply a signed number to an unsigned number. For example: global _start section .data byteVariable DB -5 section .text _start: mov al, 2 imul BYTE [byteVariable] You can replace imul with mul , and the result would still be the same ( -10 ). Are mul and imul exactly the same when multiplying a signed number to an unsigned number, or is there a difference between them? 回答1: The upper half is different, as mentioned in the comments. If

问题 I'm a beginner in X86 assembly language. I know how to read from stdin and write to stdout using build-in functions, but I'm not sure how to do it with plain assembly code(i.e. manipulating registers and taking advantage of system calls). #include <stdio.h> #include <unistd.h> int main(){ /* copy input to output */ char buf[BUFSIZ]; int n; while ((n = read(0, buf, BUFSIZ)) > 0) write(1, buf, n); return 0; } This is the C code I wrote to first read from the standard input (represented by

问题 I'm a beginner in X86 assembly language. I know how to read from stdin and write to stdout using build-in functions, but I'm not sure how to do it with plain assembly code(i.e. manipulating registers and taking advantage of system calls). #include <stdio.h> #include <unistd.h> int main(){ /* copy input to output */ char buf[BUFSIZ]; int n; while ((n = read(0, buf, BUFSIZ)) > 0) write(1, buf, n); return 0; } This is the C code I wrote to first read from the standard input (represented by

问题 I'm a beginner in X86 assembly language. I know how to read from stdin and write to stdout using build-in functions, but I'm not sure how to do it with plain assembly code(i.e. manipulating registers and taking advantage of system calls). #include <stdio.h> #include <unistd.h> int main(){ /* copy input to output */ char buf[BUFSIZ]; int n; while ((n = read(0, buf, BUFSIZ)) > 0) write(1, buf, n); return 0; } This is the C code I wrote to first read from the standard input (represented by

问题 I was reading the Intel instruction set guide 64-ia-32 guide to get an idea on memory fences. My question is that for an example with SFENCE, in order to make sure that all store operations are globally visible, does the multi-core CPU parks all the threads even running on other cores till the cache coherence achieved ? 回答1: Barriers don't make other threads/cores wait. They make some operations in the current thread wait , depending on what kind of barrier it is. Out-of-order execution of

问题 I was reading the Intel instruction set guide 64-ia-32 guide to get an idea on memory fences. My question is that for an example with SFENCE, in order to make sure that all store operations are globally visible, does the multi-core CPU parks all the threads even running on other cores till the cache coherence achieved ? 回答1: Barriers don't make other threads/cores wait. They make some operations in the current thread wait , depending on what kind of barrier it is. Out-of-order execution of

问题 I was reading the Intel instruction set guide 64-ia-32 guide to get an idea on memory fences. My question is that for an example with SFENCE, in order to make sure that all store operations are globally visible, does the multi-core CPU parks all the threads even running on other cores till the cache coherence achieved ? 回答1: Barriers don't make other threads/cores wait. They make some operations in the current thread wait , depending on what kind of barrier it is. Out-of-order execution of