x86

问题 I have a very basic program that I compiled with gcc -m32 -g -o hello32.out hello.c When I run disassemble main in gdb I get the following output: 0x0000051d <+0>: lea ecx,[esp+0x4] 0x00000521 <+4>: and esp,0xfffffff0 0x00000524 <+7>: push DWORD PTR [ecx-0x4] 0x00000527 <+10>: push ebp 0x00000528 <+11>: mov ebp,esp 0x0000052a <+13>: push ebx 0x0000052b <+14>: push ecx 0x0000052c <+15>: sub esp,0x10 0x0000052f <+18>: call 0x420 <__x86.get_pc_thunk.bx> 0x00000534 <+23>: add ebx,0x1aa4

问题 This question is a follow-up/clarification to this: Does the MOV x86 instruction implement a C++11 memory_order_release atomic store? This states the MOV assembly instruction is sufficient to perform acquire-release semantics on x86. We do not need LOCK , fences or xchg etc. However, I am struggling to understand how this works. Intel doc Vol 3A Chapter 8 states: https://software.intel.com/sites/default/files/managed/7c/f1/253668-sdm-vol-3a.pdf In a single-processor (core) system.... Reads

问题 This question is a follow-up/clarification to this: Does the MOV x86 instruction implement a C++11 memory_order_release atomic store? This states the MOV assembly instruction is sufficient to perform acquire-release semantics on x86. We do not need LOCK , fences or xchg etc. However, I am struggling to understand how this works. Intel doc Vol 3A Chapter 8 states: https://software.intel.com/sites/default/files/managed/7c/f1/253668-sdm-vol-3a.pdf In a single-processor (core) system.... Reads

问题 In intel instruction, idiv(integer divsion) means signed division. I got the result of idiv , but I don't quite understand the result. - Example 0xffff0000 idiv 0xffff1100 - My wrong prediction As long as I know, quotient should be 0, and remainder should be 0xffff0000 and because... 0xffff0000 / 0xffff1100 = 0 0xffff0000 % 0xffff1100 = 0xffff0000 - However, the result was... Before idiv eax 0xffff0000 # dividend esi 0xffff1100 # divisor edx 0x0 After idiv eax 0xfffeedcc # quotient edx 0x7400

问题 In intel instruction, idiv(integer divsion) means signed division. I got the result of idiv , but I don't quite understand the result. - Example 0xffff0000 idiv 0xffff1100 - My wrong prediction As long as I know, quotient should be 0, and remainder should be 0xffff0000 and because... 0xffff0000 / 0xffff1100 = 0 0xffff0000 % 0xffff1100 = 0xffff0000 - However, the result was... Before idiv eax 0xffff0000 # dividend esi 0xffff1100 # divisor edx 0x0 After idiv eax 0xfffeedcc # quotient edx 0x7400

问题 In x86, when you want to access a memory address, you would specify an address that would be translated into a memory address through two stages: segmentation , and paging : But is segmentation also used in x64? (I think it is not used, but I am not sure if it is not used in all cases, or are there some cases where it is used). 回答1: For the purpose of the picture you posted, segmentation is only used when the addressing mode uses the registers fs or gs (because these were being actively

问题 From https://www.felixcloutier.com/x86/div: ... temp ← AX / SRC; IF temp > FFH THEN #DE; (* Divide error *) ELSE AL ← temp; AH ← AX MOD SRC; FI; ... For div ah the SRC would be ah . IMHO temp will always be larger than FFH and therefore the exception will be raised since: AX = 256*AH+AL temp = AX / AH = (256*AH+AL)/AH = 256 + AL/AH temp is over FFH Do I miss something here? 回答1: That's correct, just like div edx it's never usable without faulting. The criterion for 2N/N => N-bit div not

问题 From https://www.felixcloutier.com/x86/div: ... temp ← AX / SRC; IF temp > FFH THEN #DE; (* Divide error *) ELSE AL ← temp; AH ← AX MOD SRC; FI; ... For div ah the SRC would be ah . IMHO temp will always be larger than FFH and therefore the exception will be raised since: AX = 256*AH+AL temp = AX / AH = (256*AH+AL)/AH = 256 + AL/AH temp is over FFH Do I miss something here? 回答1: That's correct, just like div edx it's never usable without faulting. The criterion for 2N/N => N-bit div not

问题 I am trying to learn the C Calling conventions in assembly language. To do so, I made a simple program using the puts function from the C standard library. I assembled and linked the program with the following commands :- nasm -f elf file.asm gcc -m32 file.asm -o file The nasm produces the right object file but when running the gcc to link the object files, I am getting error. Looking at the error I have figured it out that I don't have the 32 bit version of glibc on my system. How can I

问题 Like this but without the CALL instruction. I suppose that I should use JMP and probably other instructions. PUSH 5 PUSH 4 CALL Function 回答1: This is fairly easy to do. Push the return address onto the stack and then jump to the subroutine. The final code looks like this: PUSH 5 PUSH 4 PUSH offset label1 jmp Function label1: ; returns here leas esp, 8[esp] Function: ... ret While this works, you really don't want to do this. On most modern processors, an on-chip call stack return address