vlsi

问题 I'm working on a simple sign-extender in Verilog for a processor I'm creating for Computer Architecture. Here's what I've got so far: [EDIT: Changed the selection statement slightly] `timescale 1ns / 1ps module SignExtender( CLK, extend, extended ); input[7:0] extend; input CLK; output[15:0] extended; reg[15:0] extended; wire[7:0] extend; always begin while (CLK == 1) extended[7:0] = extend[7:0]; extended[15:8] = {8{extend[7]}}; end endmodule I added the while (CLK == 1) thinking that would

问题 I'm working on a simple sign-extender in Verilog for a processor I'm creating for Computer Architecture. Here's what I've got so far: [EDIT: Changed the selection statement slightly] `timescale 1ns / 1ps module SignExtender( CLK, extend, extended ); input[7:0] extend; input CLK; output[15:0] extended; reg[15:0] extended; wire[7:0] extend; always begin while (CLK == 1) extended[7:0] = extend[7:0]; extended[15:8] = {8{extend[7]}}; end endmodule I added the while (CLK == 1) thinking that would

问题 I am a newbie to verilog. I have constructed my code using integer inputs and outputs in vhdl. Now i want to construct the same code in verilog. But I came to know that the input ports in verilog cant be of integer type. What can be done. I would prefer an answer which is synthesizable. vhdl code: LIBRARY ieee; USE ieee.All; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; ENTITY adder_5 IS PORT ( a : IN integer ; b : IN integer; c : OUT integer ); END adder_5; ARCHITECTURE add

问题 I am designing a chip using Verilog. I have a 3-bit counter. I want that when the counter is in its 8th loop, there should be a clock glitch , and thereafter work normally. What could be the possible ways of producing a clock glitch in a Verilog design? 回答1: One way to inject glitches on a clock signal is to use force and release from your testbench: module tb; reg clk; reg [2:0] cnt; reg reset; always begin #5 clk <= 0; #5 clk <= 1; end always @(posedge clk or posedge reset) begin if (reset)

问题 Closed . This question needs to be more focused. It is not currently accepting answers. Closed last year . Locked . This question and its answers are locked because the question is off-topic but has historical significance. It is not currently accepting new answers or interactions. What is the difference between $display vs $strobe vs $monitor in verilog? When in the event queue does each apply, and how do the statements interact? Can any statement inhibit another? 回答1: I'll be nice and

问题 How can I calculate a floating point multiplicand in Verilog? So far, I usually use shift << 1024 , then floating point number become to integer. Then I do some operations, then >> 1024 to obtain a fraction again. For example 0.3545 = 2^-2 + 2^-4 + ... I have question about another way, like this. I don't know where does the minus (-) comes from: 0.46194 = 2^-1 - 2^-5 - 2^-7 + 2^-10. I have just look this from someone. but as you way, that is represented like this 0.46194 = 2^-2 + 2^-3 + 2^-4

问题 In verilog I have an array of binary values. How do I take the absolute value of the subtracted values ? Verilog code: module aaa(clk); input clk; reg [7:0] a [1:9]; reg [7:0] s [1:9]; always@(posedge clk) begin s[1] = a[1] - a[2]; s[2] = a[2] - a[3]; s[3] = a[1] + a[3]; end endmodule I want my s[1] and s[2] values to be always positive . How can I do it in synthesisable verilog? I have tried using signed reg , but it shows an error. 回答1: Regardless of whether the number is signed or not twos

问题 Just started learning System Verilog. I am confused about the usage of statements always_ff and always_latch . The former would be used as: always_ff @ (posedge clk) begin a <= b; end while the latter: always_latch begin a <= b; end The first is activated just by the positive edge of the clock and coupled with non-blocking assignment produces a FF. The always_latch is obviously thought to represent a latch, but then why use a non-blocking assignment? Wouldn't be better using a always_comb

问题 I am clock gating some latch and logic in my design. I don't have much experience in synthesis and place & route. What is the proper way to implement clock gating in RTL? Example1: always_comb begin gated_clk = clk & latch_update_en; end always_latch begin if(gated_clk) begin latch_data <= new_data; end end Example2: I stumbled into a RTL examples while doing some research about good practices in RTL clock gating. That example implemented the above code like this: clock_gator cg_cell (.clk

问题 At we make IC( I mean physical design in Hardware). As i know, the input reset is always Asynchronous. I wonder that What if I used Asynchronous reset, Should I have to make into synchronous? or Can we just used asynchronous reset? 回答1: In fact, if you have flip-flops, which are clocked AND asynchronously resetted, you can start reset asynchronously at any time, but you should end it synchronously. The reason for this is simple: imagine that truly async. reset ends simultaneously with the