vivado | 易学教程

Seven Segment Display outputs are unknown

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问题 I'm trying to make a counter that counts from 0-9 and displays on my Nexys A7's seven segment display. The code compiles, but in the testbench it shows that all the outputs are unknown. I tested my clock divider module, and it looks fine. I'm not sure why it isn't working. module BCD_sevenseg( input clk, output segA, segB, segC, segD, segE, segF, segG, segDP, div_clk ); counter module1( .clk(clk), .div_clk(div_clk) ); reg[3:0] BCD; //BCD signal is 4 bits wide always@(posedge clk) //check

Is there a way to pass a design parameter from a custom IP to software

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问题 I have a custom IP with some design parameters. They are exposed from the IP so I can customize them when using the IP in a block design. I want to be able to use those parameters inside my firmware code. For example when using a simple GPIO there are several parameters exposed in the xparameters.h header: #define XPAR_GPIO_0_BASEADDR 0x41200000 #define XPAR_GPIO_0_HIGHADDR 0x4120FFFF #define XPAR_GPIO_0_DEVICE_ID XPAR_GPIO_DEVICE_ID #define XPAR_GPIO_0_INTERRUPT_PRESENT 0 #define XPAR_GPIO_0

How to `rm -rf *` in TCL

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问题 I want to delete all files in a directory using TCL. (I'm using Xilinx Vivado's TCL console under Win 10.) I found that in TCL documentation that file delete ?-force? ?- -? pathname ?pathname ... ? should work. But file delete -force -- [glob *] does nothing. What's the wrong with that? 回答1: Make that file delete -force -- {*}[glob *] ... so that the path names returned by [glob] are turned into multiple arguments to [file delete] (using the expansion operator {*} ), rather than one argument

Vitis IDE invalid arguments

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问题 I'm trying to create a boot image with TCL script on xsct console. But getting error. I couldn't find where I made a mistake. I couldn't find any results in Xilinx's documents and other forums. ERROR: source /home/nmi/Desktop/load.tcl Invalid arguments, name or processor not specified setws /home/nmi/workspace platform active zc702 app create -name fsbl -hw /home/nmi/Desktop/projeHDF/base_zynq_wrapper.xsa proc ps7_cortexa9_0 -os standalone -template {Zynq FSBL} app build -name fsbl exec

VHDL: Button debouncing (or not, as the case may be)

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问题 I've read through the other posts but can't seem to fix mine. I'm new to VHDL so I'm sure it's a simple fix. In short, the button isn't debouncing. The code compiles and the bitstream programs. In the testbench, button presses work, but the output LEDs don't change. On the board, pressing a button makes random LEDs light up (I presume because of bouncing). According to the schematic the inputs are going through the debouncers. Can anyone identify the issue? And any other hints and tips are

vivado设计三：一步一步生成自己的自定义IP核

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开发环境：xp vivado2013.4 基于AXI-Lite的用户自定义IP核设计这里以用户自定义led_ip为例： 1.建立工程和设计一过程一样，见vivado设计一 http://blog.chinaaet.com/detail/35736 ：这样我们就进入了主界面 2.创建IP Tools –》Create and Package IP 来到IP创建欢迎界面：Next 接下来我们要选择AXI4 peripheral,如下图 Next之后，我们可以看到IP的信息，可以自己修改某些信息：然后修改一下Name，其余的保持默认：下面要勾选一下Generate Drivers 然后Next之后，我们选第二个：如下图点击finish，就进入了编辑IP的界面 3.编辑IP 既然是自定义IP核，那么我们需要修改led_ip_v1_0.v 双击文件，在15行添加output wire [3:0]led, 如下图所示：添加用户定义的port 接下来，将我们用户的port，连接到led_ip_v1_0_S_AXI，在48行： .LED(LED), 在led_ip_v1_0_S_AXI模块中还没有LED端口，因此展开source文件：双击图上文件：在15行添加output wire [3:0]led, 如下图所示：接下来就是新建用户逻辑文件了，user_logic.v

xilinx 芯片使用vivado 生成pin delay文件

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以v7系列芯片xc7vx690tffg1761-2为例打开vivado软件，在Tcl Console输入命令 link_design -part xc7vx690tffg1761-2 再次输入 write_csv xc7vx690tffg1761-2，其中xc7vx690tffg1761-2为CSV文件名称，可任意输入成功后，生成csv文件，文件存放路径 C:/Users/Administrator/AppData/Roaming/Xilinx/Vivado/ 打开CSV文件，其中Min Trace Delay (ps)，Max Trace Delay (ps)，两列既是，使用时可以对其取平均在使用。来源： CSDN 作者： HKdota 链接： https://blog.csdn.net/u012654584/article/details/104921700

vivado生成bit流失败的解决办法

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vivado2017.4生成比特流失败，报错信息： [Drc 23-20] Rule violation (NSTD-1) Unspecified I/O Standard - 4 out of 142 logical ports use I/O standard (IOSTANDARD) value ‘DEFAULT’, instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To

1. Vivado 常用 tcl 命令 &GUI

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在 Vivado 中用 tcl 命令非常强大。例如可以把整个工程导出到.tcl文件，非常方便分发、备份。 1(a).把工程保持成.tcl文件 tcl: write_project_tcl c:/vivado_project/pro.tcl gui: File->Project->Write tcl...，然后选择tcl路径即可。注意：最好把.tcl中列出的依赖文件（.v, .sdc, .wcfg等）拷贝到.tcl文件的目录下，然后在.tcl文件中修改这些文件的路径，这样整个工程就可以分发了，无需依赖原工程。 # The following source(s) files that were local or imported into the original project. # (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script) # "C:/emac_pcs_pma_udp_test-2019-02-19_final/emac_pcs_pma_udp_test/emac_pcs_pma_udp_test.srcs/sources_1/new/pxi_interface.v" # "C:/emac_pcs_pma_udp

Vivado学习使用构建加法器

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实验步骤： 1、首先双击打开Vivado软件，然后点击File，选择New project，在如下界面中选择储存的文件地址并输入工程文件名为adder，然后按照下面各图的顺序往下进行（同时还需要新建一个add文件）然后新建一个adder.v（也需要新建一个add.v）文件，并写入给定的程序，随后在旁边的工具栏中找到Add Sources,添加已经写好的源文件：随后编写另外一个文件，同时完成仿真文件：点击Add sources选择Add or create simulation sources 点击next，再选择Create File，选择文件保存的地址，文件名设置为si_adder 在主界面找到仿真文件,点开就会看到新建的仿真文件，并填写好，点击Run Simulation中的Run Behavioral Simulation。随后可以看综合仿真后的文件和信息同时在控制台可以看到输出的数字信息来源： CSDN 作者： ZhangLH66 链接： https://blog.csdn.net/ZhangLH66/article/details/104594138