问题
I'm trying to make a counter that counts from 0-9 and displays on my Nexys A7's seven segment display. The code compiles, but in the testbench it shows that all the outputs are unknown. I tested my clock divider module, and it looks fine. I'm not sure why it isn't working.
module BCD_sevenseg(
input clk,
output segA, segB, segC, segD, segE, segF, segG, segDP, div_clk
);
counter module1(
.clk(clk),
.div_clk(div_clk)
);
reg[3:0] BCD; //BCD signal is 4 bits wide
always@(posedge clk) //check every positive edge
if(div_clk) //executes if counter value from module1 is true
BCD <= (BCD == 4'h9 ? //check if BCD is at binary 9
4'h0 : BCD + 4'h1 );
//true: reset to 0
//false: count up
reg [7:0] sevenseg; //8 segments on 7 segment display (w/ decimal point)
always@(*)
case(BCD) //one case for each digit
4'h0: sevenseg = 8'b11111100;
4'h1: sevenseg = 8'b01100000;
4'h2: sevenseg = 8'b11011010;
4'h3: sevenseg = 8'b11110010;
4'h4: sevenseg = 8'b01100110;
4'h5: sevenseg = 8'b10110110;
4'h6: sevenseg = 8'b10111110;
4'h7: sevenseg = 8'b11100000;
4'h8: sevenseg = 8'b11111110;
4'h9: sevenseg = 8'b11110110;
default: sevenseg = 8'b00000000;
endcase
assign {segA, segB, segC, segD, segE, segF, segG, segDP} = sevenseg;
endmodule
Clock divider:
module counter(
input clk,
output reg div_clk=0
);
integer count_value=0;
always@(posedge clk)
begin
if(count_value == 10)//change this number to adjust output signal frequency
begin
div_clk = ~div_clk;
count_value <= 0;
end
else
count_value <= count_value+1;
end
endmodule
Testbench code:
module BCD_sevenseg_tb();
reg clk=0;
wire segA, segB, segC, segD, segE, segF, segG, segDP, div_clk;
BCD_sevenseg UUT(
.clk(clk),
.segA(segA),
.segB(segB),
.segC(segC),
.segD(segD),
.segE(segE),
.segF(segF),
.segG(segG),
.segDP(segDP),
.div_clk(div_clk)
);
always
#1 clk=~clk;
endmodule
回答1:
Your outputs are always X because BCD
is always X. You declared BCD
as a reg
, which defaults to X. You need to initialize BCD
to a known value, such as 0.
For simulation purposes, you can do this simply with:
reg[3:0] BCD = 0; //BCD signal is 4 bits wide
A standard way to initialize signals is to use a reset input signal. For example:
always @(posedge clk) begin
if (reset) begin
BCD <= 4'h0;
end else begin
if (div_clk) BCD <= (BCD == 4'h9 ? 4'h0 : BCD + 4'h1 );
end
end
来源:https://stackoverflow.com/questions/64341353/seven-segment-display-outputs-are-unknown