vhdl

问题 Let's say I have 3 control signals A, B and C. In the testbench is there a function in VHDL to group this and iterate all cases quickly (to enable them to be iterated with a for loop for example) rather than write out 8 cases. Psuedo code example: for i in range 0 to 7 grouped_signals <=std_logic_vector(to_unsigned(i,3) 回答1: It can be a signal assignment where the target is an aggregate: library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity agg_assign is end entity;

问题 I’ve done many projects on this software and I want to delete a big ammount of libraries that are useless and now are giving me errors to simulate my new projects I think the best option is to delete old files(libraries). 回答1: You can either: delete the matching directories on disk and edit the modelsim.ini file(s) by hand, or use vdel.exe . Usage of vdel : PS> .\vdel.exe -h Usage: vdel -help vdel [-lib <path>] [-modelsimini <ini_filepath>] [-verbose] { -all | <primary> [<secondary>] |

问题 This has me bugging for quite some time, but is it possible to describe entities in VHDL similar to how templates work in C++ (or to lesser extend generics?). Simply leaving the actual port types to be only decided during synthesize/compilation? An example would be a multiplexer, say I have a 4 input multiplexer, now I have several bus sizes I use this multiplexer for, -4,6,7,8-. Currently I wrote a different multiplexer for each different bus size; however the output is simply one of the

问题 Closed . This question needs to be more focused. It is not currently accepting answers. Want to improve this question? Update the question so it focuses on one problem only by editing this post. Closed 9 days ago . Improve this question We are using a DS18B20 temperature sensor (1 Wire Communication ) .The Sensor has 3 interfaces VCC,GND , and output in Digital formant How can we display the Output on the 7 segment Display . Should we use STD_LOGIC_VECTOR ?.Note : We will be using an FPGA not

问题 Closed . This question needs to be more focused. It is not currently accepting answers. Want to improve this question? Update the question so it focuses on one problem only by editing this post. Closed 9 days ago . Improve this question We are using a DS18B20 temperature sensor (1 Wire Communication ) .The Sensor has 3 interfaces VCC,GND , and output in Digital formant How can we display the Output on the 7 segment Display . Should we use STD_LOGIC_VECTOR ?.Note : We will be using an FPGA not

问题 I am a newbie to verilog. I have constructed my code using integer inputs and outputs in vhdl. Now i want to construct the same code in verilog. But I came to know that the input ports in verilog cant be of integer type. What can be done. I would prefer an answer which is synthesizable. vhdl code: LIBRARY ieee; USE ieee.All; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; ENTITY adder_5 IS PORT ( a : IN integer ; b : IN integer; c : OUT integer ); END adder_5; ARCHITECTURE add

来源： https://stackoverflow.com/questions/37861806/how-to-do-a-vector-product-in-vhdl

来源： https://stackoverflow.com/questions/37861806/how-to-do-a-vector-product-in-vhdl

问题 I want to know if it is possible to convert a enum type, like FSM states to std_logic_vector or integer. I'm doing a testbench with OSVVM for a FSM and I want to use the scoreboard package to automatically compare the expected state with the actual one. Thanks! 回答1: To convert to integer, use: IntVal := StateType'POS(State) ; From there, it is easy to convert to std_logic_vector, but I prefer to work with integers when possible as they are smaller in storage than std_logic_vector. For

问题 I want to know if it is possible to convert a enum type, like FSM states to std_logic_vector or integer. I'm doing a testbench with OSVVM for a FSM and I want to use the scoreboard package to automatically compare the expected state with the actual one. Thanks! 回答1: To convert to integer, use: IntVal := StateType'POS(State) ; From there, it is easy to convert to std_logic_vector, but I prefer to work with integers when possible as they are smaller in storage than std_logic_vector. For