Convert enum type to std_logic_vector VHDL

问题

I want to know if it is possible to convert a enum type, like FSM states to std_logic_vector or integer. I'm doing a testbench with OSVVM for a FSM and I want to use the scoreboard package to automatically compare the expected state with the actual one.

Thanks!

回答1:

To convert to integer, use:

IntVal := StateType'POS(State) ;

From there, it is easy to convert to std_logic_vector, but I prefer to work with integers when possible as they are smaller in storage than std_logic_vector. For verification, it will be easier if you start to think more about integers when the value is less than 32 bits.

If you need it as std_logic_vector, using only numeric_std you can:

Slv8Val := std_logic_vector(to_unsigned(IntVal, Slv8Val'length)) ;

For verification, I liberally use numeric_std_unsigned, so the conversion is a easier:

Slv8Val := to_slv(IntVal, Slv8Val'length) ;

In the event you have an integer and want to convert it back to a enumerated value, you can use 'VAL.

State := StateType'VAL(IntVal) ;

In OSVVM, we use records with resolved values to create a transaction interface. We have a resoled types for integers (osvvm.ResolutionPkg.integer_max). We transfer enumerated values through the record using 'POS (as we put it in) and 'VAL (as we get it out).

Note don't confuse 'VAL with 'VALUE. 'VALUE converts a string to a value - opposite to 'IMAGE.

You of course learn all of this in SynthWorks' OSVVM class :).

回答2:

Maybe like this...

function my_func(inp : t_my_enum) return integer is
begin
    case inp is
        when stateA =>
            return 1;
        when stateB =>
            return 2;
        when others =>
            return 0;
    end case;
end function my_func;

... <= my_func(stateB);`

来源：https://stackoverflow.com/questions/42254941/convert-enum-type-to-std-logic-vector-vhdl

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vhdl