vhdl

问题 I can print an integer as decimal to stdout with: library std; use std.textio.all; entity min is end min; architecture behav of min is begin process is variable my_line : line; begin write(my_line, 16); writeline(output, my_line); wait; end process; end behav; which outputs: 16 But how to output instead either: 10 0x10 回答1: Assuming an integer i , and VHDL-2008, you could use: write(output, integer'image(i) & LF); -- Plain integer value write(output, "0x" & to_hstring(to_signed(i, 32)) & LF);

问题 I can print an integer as decimal to stdout with: library std; use std.textio.all; entity min is end min; architecture behav of min is begin process is variable my_line : line; begin write(my_line, 16); writeline(output, my_line); wait; end process; end behav; which outputs: 16 But how to output instead either: 10 0x10 回答1: Assuming an integer i , and VHDL-2008, you could use: write(output, integer'image(i) & LF); -- Plain integer value write(output, "0x" & to_hstring(to_signed(i, 32)) & LF);

问题 I can print an integer as decimal to stdout with: library std; use std.textio.all; entity min is end min; architecture behav of min is begin process is variable my_line : line; begin write(my_line, 16); writeline(output, my_line); wait; end process; end behav; which outputs: 16 But how to output instead either: 10 0x10 回答1: Assuming an integer i , and VHDL-2008, you could use: write(output, integer'image(i) & LF); -- Plain integer value write(output, "0x" & to_hstring(to_signed(i, 32)) & LF);

问题 I can print an integer as decimal to stdout with: library std; use std.textio.all; entity min is end min; architecture behav of min is begin process is variable my_line : line; begin write(my_line, 16); writeline(output, my_line); wait; end process; end behav; which outputs: 16 But how to output instead either: 10 0x10 回答1: Assuming an integer i , and VHDL-2008, you could use: write(output, integer'image(i) & LF); -- Plain integer value write(output, "0x" & to_hstring(to_signed(i, 32)) & LF);

问题 (Yes I know there's an easier way, yes my professor is asking for the long way.) The following is the code for my 1 bit adder/subtractor. library ieee; use ieee.std_logic_1164.all; entity FA1Bit is port(x,y,Cin: in std_logic; op: in std_logic; S, Cout: out std_logic); end FA1Bit; architecture FA1Bit_arch of FA1Bit is begin behavior : PROCESS(op,x,y,Cin) begin if op = '0' then --if we're adding the bits; if Cin = '0' then if x = y then S <= '0'; if (x= '1' and y = '1') then Cout <= '1'; else -

问题 im pretty new to the vhdl language so please bear with me. I just did the vhdl code for a 1 bit adder, but I am having trouble writing for the 4bit adder. This is what I got so far, if anybody could point me in the right direction of what to look up that would be awesome! VHDL code: LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY Adder4 IS GENERIC(CONSTANT N: INTEGER := 4); PORT( a, b: IN STD_LOGIC_VECTOR(N-1 DOWNTO 0); -- Input SW[7..4]: a[3..0] inputs, -- SW[3..0]: b[3..0] sum: OUT STD

问题 Here is my code and it's pretty simple. I'm to cycle through the first 8 letters of the alphabet on a Altera Cyclone II board. entity lettercycle is port( SW : in std_logic; -- toggle switch HEX0 : out std_logic_vector(6 downto 0) -- 7-segment display ); end lettercycle; architecture behavioural of lettercycle is signal counter : integer range 0 to 7 := 0; begin process type SEGMENT_ARRAY is array (0 to 7) of std_logic_vector(6 downto 0); variable SEVENSEG : SEGMENT_ARRAY := ("0001000",

问题 I work in a VHDL program and I need to do a RAM 256 using the ALTERA DE2-115. The outputs will show in a seven segment display. The problem is that: I have a dataout output variable. Then the variable has the following values of the temp_ram array: dataout <= temp_ram(conv_integer(dir)); Then I want to divide the vaules of dataout to put in the seven segment dataout(7 downto 4) dataout(3 downto 0) This shows the following error: Error (10309): VHDL Interface Declaration error in RAM.vhd(45):

问题 Let's say I have 3 control signals A, B and C. In the testbench is there a function in VHDL to group this and iterate all cases quickly (to enable them to be iterated with a for loop for example) rather than write out 8 cases. Psuedo code example: for i in range 0 to 7 grouped_signals <=std_logic_vector(to_unsigned(i,3) 回答1: It can be a signal assignment where the target is an aggregate: library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity agg_assign is end entity;

问题 In order to catch more bugs in simulation, it is an advantage to get a warning if std_logic with 'X' is used in = compare. When using the ieee.std_logic_1164 package, the std_logic compare function = does not warn about 'X' in either of the operands. So the ´if´ branch in the code below is taken when sl_i is '1' , but the else branch is taken when sl_i is either of '0' , 'X' , etc.: if sl_i = '1' then sl_o <= '1'; else -- sl_i in "UX0ZWLH-" sl_o <= '0'; end if; So for example an 'X' or 'U' ,