synopsys-vcs

问题 Signal driver_a is reassigned in the always block back to 0, but why is the always block not activating and assign value to driver_b ? always @(driver_a) begin driver_b = driver_a; driver_a = 0; end initial begin driver_a = 0; driver_b = 0; #2 driver_a = 8'h8; #2 driver_a = 8'hf; end In the waveform, I expect that after driver_a assigns its value to driver_b, then in the next line when driver_a gets assigned to 0, I'd expect the always block to reactivate and assign value 0 back to driver_b.

问题 Is there way to get system time in VCS/UVM ? I am looking for something similar to Perl's localtime(time) . Is there way to print system time for every uvm_info printed ? 回答1: One way is to use $system() to run any system command, including system' date command. initial begin $system("date"); end From IEEE 1800 LRM: $system makes a call to the C function system(). The C function executes the argument passed to it as if the argument was executed from the terminal. $system can be called as

问题 In some EDA tool's Tcl script (i.e Cadence Enounter), what does the double :: do? report::TimeStamp PrePlace "START PrePlace" 回答1: It separates the namespace (on the left) from the name (on the right) contained in that namespace. Since in a Tcl script any top-level construct is always a command, and the command's name is always the first word of the command, your report::TimeStamp refers to a command named "TimeStamp" in a namespace named "report" while "PrePlace" and "START PrePlace" are two