mmu

I enabled MMU on my s3c2440 board (3G - 4G memory :: the fault attribute),everything was just fine when I didn't read/write 3G - 4G memory .So to test the page fault vector ,I wrote to a 0xFF to the 3G address,as I expected ,I got the right value from FSR ,So I did this in _do_page_fault (), the step was like this : ..... // set new page to translation table ..... invlidate_icache (); // clear icache clr_dcache (); // wb is used ,clear dcache invalidate_ttb (); // invalidate translation table and then ISR_dataabort returned ,I read the 3G address to get the 0xFF which I wote before .

As per pgtable-2-level.h , ARM Linux has two version of PTE; The Linux PTE and H/W PTE. Linux PTE are stored on below a offset of 1024 bytes. When handling page fault in handle_pte_fault various function like pte_file , pte_mkdirty , pte_mkyoung , get invoke with the version H/W PTE. But actually ARM H/W does not support the dirty, accessed and file bit in its PTE. My question is how does it check the dirty, accessed, file bit of a page on H/W PTE? Ideally it should check those bit on Linux PTE which are stored below an offset of 1024 bytes? artless noise My question is how does it check the

In the book "Low-Level Programming: C, Assembly, and Program Execution on Intel® 64 Architecture" I read: Each virtual 64-bit address (e.g., ones we are using in our programs) consists of several fields. The address itself is in fact only 48 bits wide; it is sign-extended to a 64-bit canonical address. Its characteristic is that its 17 left bits are equal. If the condition is not satisfied, the address gets rejected immediately when used. Then 48 bits of virtual address are transformed into 52 bits of physical address with the help of special tables. Why is the difference in 4 bits between the