mmu | 易学教程

How MTRR registers implemented? [closed]

阅读更多关于 How MTRR registers implemented? [closed]

问题 Closed. This question is off-topic. It is not currently accepting answers. Want to improve this question? Update the question so it's on-topic for Stack Overflow. Closed 7 years ago . x86/x86-64 exposes MTRR (Memory-type-range-register) that can be useful to designate different portions of physical address space for different usages (e.g., Cacheable, Unchangeable, Writecombining, etc.). My question is is anybody knows how these constrained on physical address space as defined by the MTRRs are

ARM MMU and ARM Linux page table walk

阅读更多关于 ARM MMU and ARM Linux page table walk

问题 I am little confused about how linux takes advantage of ARMv7 MMU hardware for its 3 level page table walk. MMU has only 2 registers ttbr0 and ttbr1 (one for kernel and other for user-space). How does mmu know know multi-level page table walk of linux? Thanks, Hvr 回答1: If the upper N bits of the virtual address are all zero then the translation starts at TTBR0 else TTBR1 . N comes from the TTBCR . The TTBRn registers contain the physical address of the base of the first-level table. The

Setting up a bounds-protected array

阅读更多关于 Setting up a bounds-protected array

问题 I'd like to allocate an array and set it up such that the pages before and after it are protected by the memory management unit, so an attempt to run over the bounds of the array will be automatically caught; and then catch it in order to handle the error in a controlled fashion. I doubt there will be a portable solution, but what's the best platform specific method using Microsoft C on Windows and GCC on Linux respectively? 回答1: Actually, there is a portable way to detect memory allocation

What is PDE cache?

阅读更多关于 What is PDE cache?

问题 I have the following specifications of an ARM based SoC: L1 Data cache = 32 KB, 64 B/line, 2-WAY, LRU L2 Cache = 1 MB, 64 B/line, 16-WAY L1 Data TLB (for loads): 32 entries, fully associative L2 Data TLB: 512 entries, 4-WAY PDE Cache: 16 entries (one entry per 1 MB of virtual space) And I wonder what is the PDE cache? I guess it's something similar to TLB, but I'm not sure. Answer It seems that PDE (Page Directory Entry) is Intermediate table walk cache which indeed can be implemented

In context of ARMv7 what is the advantage of Linux kernel one to one mapped memory when mmu has to do a page table translation

阅读更多关于 In context of ARMv7 what is the advantage of Linux kernel one to one mapped memory when mmu has to do a page table translation

问题 Linux kernel virtual address are one-to-one mapped. So by subtracting a PAGE_OFFSET to virtual address we will get the physical address. That is how virt_to_phys and phys_to_virt are implemented in memory.h. My question is what is the advantage of these one to one mapping on the armv7 mmu, when the mmu has to do the page table translation when there is a TLB miss? Is the only advantage of one to one mapping so that S/W can directly gets the physical address of respective virtual address by

Use ARM TrustZone to prevent access to memory region from Non-Secure world

阅读更多关于 Use ARM TrustZone to prevent access to memory region from Non-Secure world

问题 Context I want to have a rich GNU/Linux OS running in the Normal world and a small OS with an integrated Monitor running in the Secure world . Requirement We have to absolutely avoid the Normal world to access the Secure world memory region. Question Which feature(s) of TrustZone do we need to use/activate to fulfill this requirement? I'd like to use only the necessary features to minimize the work needed. Details I've read quite a lot of ARM TrustZone documentation, I'm aware of TZPC , TZASC

第 17 章计算机体系结构基础

阅读更多关于第 17 章计算机体系结构基础

一、参考网址　　1、 linux C编程一站式学习二、笔记　　1、一级cache与二级cache的区别　　　　一级缓存是用VA寻址的，二级缓存是用PA寻址的，这是它们的区别　　2、VA（虚拟地址）和PA（物理地址）的区别　　　　CPU执行单元发出的内存地址将被MMU截获，从CPU到MMU的地址称为虚拟地址（Virtual Address，以下简称VA），而MMU将这个地址翻译成另一个地址发到CPU芯片的外部地址引脚上，也就是将VA映射成PA（Physical Address）　　3、MMU 　　　　1）MMU将VA映射到PA是以页（Page）为单位的，32位处理器的页尺寸通常是4KB 　　　　2）物理内存中的页称为物理页面或者页帧（Page Frame）　　　　3）虚拟内存的哪个页面映射到物理内存的哪个页帧是通过页表（Page Table）来描述的，页表保存在物理内存中，MMU会查找页表来确定一个VA应该映射到什么PA 　　　　4） MMU除了做地址转换之外，还提供内存保护机制　　　　 5|）x86平台的虚拟地址空间是0x0000 0000~0xffff ffff，大致上前3GB（0x0000 0000~0xbfff ffff）是用户空间，后1GB（0xc000 0000~0xffff ffff）是内核空间来源： https://www.cnblogs.com

ARM: Disabling MMU and updating PC

阅读更多关于 ARM: Disabling MMU and updating PC

问题 In short, I would like to shut down all MMU (and cache) operations in a Linux context (from inside the Kernel), for debug purposes, just to run some tests. To be perfectly clear, I don't intend that my system still be functional after that. About my setup: I'm currently fiddling with a Freescale Vybrid (VF610) - which integrates a Cortex A5 - and its low power modes. Since I'm experimenting some suspiciously local memory corruption while the chip is in "Low Power Stop" mode and my DDR3 in

What is the downside of updating ARM TTBR(Translate Table Base Register)?

阅读更多关于 What is the downside of updating ARM TTBR(Translate Table Base Register)?

问题 This question is related to this one: While "fork"ing a process, why does Linux kernel copy the content of kernel page table for every newly created process? I found that Linux kernel tries to avoid updating TTBR when switching between user land and kernel land by copying the content of swapper page table into every newly created page table in function pgd_alloc . Question is: What is the downside of updating ARM TTBR? 回答1: Updating the TTBR (translation table base register) Note1 with the

Linux x86: Where is the real mode address space mapped to in protected kernel mode?

阅读更多关于 Linux x86: Where is the real mode address space mapped to in protected kernel mode?

问题 In Linux running on an x86 platform where is the real mode address space mapped to in protected kernel mode? In kernel mode, a thread can access the kernel address space directly. The kernel is in the lower 8MB, The page table is at a certain position, etc (as describe here). But where does the real mode address space go? Can it be accessed directly? For example the BIOS and BIOS addons (See here)? 回答1: (My x86-fu is a bit weak. I'll add some tags so that other people can (hopefully) correct