问题
I am little confused about how linux takes advantage of ARMv7 MMU hardware for its 3 level page table walk. MMU has only 2 registers ttbr0 and ttbr1 (one for kernel and other for user-space). How does mmu know know multi-level page table walk of linux?
Thanks, Hvr
回答1:
If the upper N bits of the virtual address are all zero then the translation starts at TTBR0 else TTBR1. N comes from the TTBCR. The TTBRn registers contain the physical address of the base of the first-level table. The appropriate entry of the first-level table is loaded and various bits of the entry determine if the translation uses a second-level table and if so what its physical address is.
The MMU can be configured to use Short Descriptors (32-bit physical addresses) or Long Descriptors (40-bit physical addresses). When using short descriptors, at most only two-levels of translation table can be used. When using long descriptors, there can be three levels.
This ignores stage 2 translations (Hypervisors). All is documented in the ARMARM for v7-A&R section B3.3: http://infocenter.arm.com/help/topic/com.arm.doc.ddi0406c/index.html
来源：https://stackoverflow.com/questions/28019266/arm-mmu-and-arm-linux-page-table-walk