intel-fpga

问题 module controle(clock, reset, funct, opcode, overflow, PCW, PCCondW, PCDataW, PCSrc, EPCW, AluOutW, MemRegW, AluOp, AluSrcA, AluSrcB, BShift, BSrc, ShamtSrc, AW, RegW, RegDst, RegSrc, Loads, Stores, IRW, MemW, IorD, LSE); input [5:0] opcode, funct; input overflow, clock; output reg AW, IRW, MemW, MemRegW, EPCW, AluOutW, PCW, PCCondW, AluSrcA, BSrc, RegW, LSE, reset; output reg [2:0] BShift, PCDataW, Loads, PCSrc, RegSrc; output reg [1:0] ALuSrcB, Stores, AluOp, ShamtSrc, IorD, RegDst;

问题 I am using Quatus 2 Prime 16.1 Lite version. what i am trying to do as follows, I have compiled float_pkg_c,fixed_pkg_c under ieee_proposed library as in shown in below link in comment. and i am using to_float to convert real variable to std logic vector as follows, phi_c <= to_std_logic_vector( to_float(phi_c_F, float32'high, -float32'low) ); below phi_c_F is a variable which is to be calculated using sin, arcsin of math_real library.and i found operators in math_real non-synthesize, and i

问题 The following VHDL is to be used to test bench. I keep getting an error on the first wait statement during analysis : "wait statement must contain condition clause with UNTIL keyword" I have several working test benches written this way. I can't seem to find what the error might be. `library IEEE; USE IEEE.std_logic_1164.all; entity case_ex_TB is end; architecture simple_test of case_ex_TB is --- DUT Component Declaration --- component case_ex port( clk, rstN: IN std_logic; color: OUT std

问题 I have an issue with self implemented UART in VHDL. I wrote VHDL code which generates proper waveform when running on Altera ModelSim: UART.vhd: LIBRARY ieee; USE ieee.std_logic_1164.all; use ieee.numeric_std.ALL; entity UART is port ( clk_10mhz: in STD_LOGIC; uart_clk: out STD_LOGIC; txPin: out STD_LOGIC ); end entity; architecture Test of UART is signal txStart: STD_LOGIC := '0'; signal txIdle: STD_LOGIC; signal txData: STD_LOGIC_VECTOR(7 downto 0); component TX is port ( clk_in: in STD

问题 I am very new to VHDL and am trying to figure out how to do something fairly basic on an Altera Cyclone II. The FPGA has four push buttons - two of them need to be programmed to increase and decrease the selected register (0-F), and the two need to be programmed to increase and decrease the value (from 00 to FF) that will be in that register. Here is what I have so far: entity raminfr is port ( clk : in std_logic; we : in std_logic; a : in unsigned(3 downto 0); di : in unsigned(7 downto 0);

问题 I am very new to VHDL and am trying to figure out how to do something fairly basic on an Altera Cyclone II. The FPGA has four push buttons - two of them need to be programmed to increase and decrease the selected register (0-F), and the two need to be programmed to increase and decrease the value (from 00 to FF) that will be in that register. Here is what I have so far: entity raminfr is port ( clk : in std_logic; we : in std_logic; a : in unsigned(3 downto 0); di : in unsigned(7 downto 0);

问题 I've downloaded the floating point package from http://www.vhdl.org/fphdl/ and did the following: I included the math_utility_pkg.vhd, fixed_pkg_c.vhd and float_pkg_c.vhd files in my project I assigned them to a library (following the instructions in Compiling *.vhdl into a library, using Altera Quartus II) tried to compile them, first by setting my project's top entity as top entity and the second time by setting float_pkg_c.vhd as top entity I'v encountered several issues: I'm not sure

问题 I am trying to use 'Floating point and Fixed point package' as a part of my filter design in VHDL. I am using Altera Quartus II as the development environment. I downloaded the file package from the website: http://www.vhdl.org/fphdl/, now available at http://web.archive.org/web/20160305202256/http://www.vhdl.org/fphdl/ In their user guide, below is mentioned: 'fixed_float_types_c.vhdl', 'fixed_pkg_c.vhdl' and 'float_pkg_c.vhdl' should be compiled into a library called "ieee_proposed".

问题 I am trying to make an alarm clock for a final project in one of my classes. I am using push buttons on a DE1 Altera board to manually increment hours and mins. The mins work but I can not get the hours to increment manually. All pin assignments are correct. library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity ClkMain is port ( clk,pb_hr,pb_min,clk_set,almr_enbl: in std_logic; almr_hr: in integer range 0 to 23; almr_min: in integer

问题 What I want to achieve I try to set up a toolchain to compile OpenCL applications for Intel FPGAs. Therefore beneath building the C++ based host application I need to invoke the Intel OpenCL offline compiler for OpenCL kernels. This step should only take place if the cl source file was edited or the resulting binaries are missing. My approach is to add a custom command to invoke the CL compiler and create a custom target that depends on the output generated by this command. The offline Open