Altera FPGA hardware (has an issue) vs ModelSim simulation (ok) - self implemented UART

问题

I have an issue with self implemented UART in VHDL.

I wrote VHDL code which generates proper waveform when running on Altera ModelSim:

UART.vhd:

LIBRARY ieee;
    USE ieee.std_logic_1164.all;
    use ieee.numeric_std.ALL;

entity UART is
    port (
        clk_10mhz: in STD_LOGIC;
        uart_clk: out STD_LOGIC;
        txPin: out STD_LOGIC
    );
end entity;

architecture Test of UART is
    signal txStart: STD_LOGIC := '0';
    signal txIdle: STD_LOGIC;
    signal txData: STD_LOGIC_VECTOR(7 downto 0);

    component TX is
        port (
            clk_in: in STD_LOGIC;
            start: in STD_LOGIC;
            data: in STD_LOGIC_VECTOR(7 downto 0);
            tx: out STD_LOGIC;
            txIdle: out STD_LOGIC;
            debug_clk: out STD_LOGIC
        );
    end component TX;


begin
    process (clk_10mhz) 
        variable clkDividerCounter : integer range 0 to 10000000;
        variable textToSend : string(1 to 31) := "Hello darkness my old friend!" & LF & CR; 
        variable currentCharacterIndex : integer range 1 to 31 := 1;
        variable startSending : std_logic := '0';
        variable characterReceivedByTX : std_logic := '1';
    begin       
        if (rising_edge(clk_10mhz)) then
            if (startSending = '1') then
                if (txIdle = '0') then
                    characterReceivedByTX := '1';
                end if;

                if (txIdle = '1' and characterReceivedByTX = '1') then
                    txData <= std_logic_vector(to_unsigned(character'pos(textToSend(currentCharacterIndex)), 8));
                    txStart <= '1';

                    if (currentCharacterIndex < 31) then
                        currentCharacterIndex := currentCharacterIndex + 1;
                        characterReceivedByTX := '0';
                    else 
                        txStart <= '0';
                        currentCharacterIndex := 1;
                        startSending := '0';
                    end if;
                end if;
            else
                if (clkDividerCounter < 10000000) then
                    clkDividerCounter := clkDividerCounter + 1;
                    startSending := '0';
                else
                    clkDividerCounter := 0;
                    startSending := '1';
                end if;
            end if;
        end if;
    end process;


    u1: TX port map (clk_10mhz, txStart, txData, txPin, txIdle, uart_clk);
end Test;

TX.vhd:

LIBRARY ieee;
    USE ieee.std_logic_1164.all;
    use ieee.numeric_std.ALL;

entity TX is
    port (
        clk_in: in STD_LOGIC;
        start: in STD_LOGIC;
        data: in STD_LOGIC_VECTOR(7 downto 0);

        tx: out STD_LOGIC := '1';
        txIdle: out STD_LOGIC := '1';
        debug_clk: out STD_LOGIC := '0'

    );
end entity;

architecture Test of TX is
    signal idle: STD_LOGIC := '1';
begin
    process (clk_in) 
        variable bitIndex : integer range 0 to 9;
        variable clkDividerCounter : integer range 0 to 1042;

        variable dataFrame : STD_LOGIC_VECTOR(9 downto 0);
        variable dataFrameCurrentIndex : integer range 0 to 9;
    begin
        if (rising_edge(clk_in)) then
            if (start = '1' and idle = '1') then
                dataFrame(0) := '0';
                dataFrame(8 downto 1) := data;
                dataFrame(9) := '1';

                dataFrameCurrentIndex := 0;

                idle <= '0';
            end if;


            if (idle = '0') then                
                if (clkDividerCounter < 521) then
                    debug_clk <= '0';
                else
                    debug_clk <= '1';
                end if;

                if (clkDividerCounter < 1041) then
                    clkDividerCounter := clkDividerCounter + 1;
                else
                    if (dataFrameCurrentIndex < 9) then
                        tx <= dataFrame(dataFrameCurrentIndex);
                        dataFrameCurrentIndex := dataFrameCurrentIndex + 1;
                    else 
                        tx <= dataFrame(dataFrameCurrentIndex);
                        idle <= '1';
                    end if;

                    clkDividerCounter := 0;
                end if;
            else
                debug_clk <= '0';
            end if;

        end if;
    end process;


    txIdle <= idle; 
end Test;

Unfortunately, on hardware, instead of "Hello darkness my old friend!" sent, it sends "HHello darkness my old friend!" with double H at the beginning.

I checked it on SignalTap II and waveform confirms the problem:

What can cause this problem? How may I debug such an issue?

来源：https://stackoverflow.com/questions/37401890/altera-fpga-hardware-has-an-issue-vs-modelsim-simulation-ok-self-implement