intel-fpga

ModelSim - Simulating Button Presses

由 别来无恙 提交于 2019-12-12 03:44:52
问题 I want to use four push buttons as inputs and three seven-segment LED displays as outputs. Two push buttons should step up and down through the sixteen RAM locations; the other two should increment and decrement the contents of the currently-displayed memory location. I am now trying to simulate my design using ModelSim test benches, with button presses. Here is what I believe to be the relevant portions of my code: library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity

Verilog Error: Object on left-hand side of assignment must have a variable data type

由 拜拜、爱过 提交于 2019-12-12 02:23:52
问题 I'm trying to write a top-level module in Verilog that will open a water valve whenever a sensor reads values below a certain number. Here is my code: module ProjectDSD(alteraClock, sensorInput, openValve); input sensorInput, alteraClock; output openValve; always @(sensorInput) begin if(sensorInput < 100) //sensor value to irrigate at begin openValve <= 1; //here end else begin openValve <= 0; //here end end endmodule Im getting an error saying: Object "openValve" on left-hand side of

Behavioral to Structural Conversion Problems VHDL

由 爱⌒轻易说出口 提交于 2019-12-11 22:06:58
问题 I designed a primality testing for Rabin Miller algorithm in behavioral type. I used functions to create my modules. Unfortunately, when I tried to synthesize it by my Altera Kit via Quartus, I realized that function are not synthesize. Here I will write my whole program, and I really need you help to give me at least some hints to change it to structural as it is my senior design project. Here is my program: library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity

How to develop this algorithm?

由 血红的双手。 提交于 2019-12-11 19:44:30
问题 pollkey() should be called every millisecond and tick(&timeloc) should be called every second and I don't have a thread library. The obvious way would be to do it with threads but now it seems that I need advice how to perform both the updates. The code I'm trying is int main() { while (TRUE) { pollkey(); puttime(&timeloc); delay(1); IOWR_ALTERA_AVALON_PIO_DATA(DE2_PIO_REDLED18_BASE, timeloc); if (RUN == 1) { tick(&timeloc); puthex(timeloc); } } return 0; } But I don't think that the above is

VHDL - DE0 - QUARTUS II PLL not showing output in modsim

由 微笑、不失礼 提交于 2019-12-11 00:49:13
问题 Hi I am trying to use a phased lock loop for clock generation for a VGA controller. I had no luck and decided to make my own clock which then worked fine. I got the VGA controller working. Going back to PLL's though I still can't get a PLL selected to give me an output. I have made a little test model to simulate it. LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; ENTITY PLL4 IS PORT ( clk : IN std_logic; a : IN std_logic; rst : IN std_logic:='0'; x : OUT std_logic ); END ENTITY PLL4; ARCHITECTURE

Can't infer register for … at … because it does not hold its value outside the clock edge

由 孤者浪人 提交于 2019-12-10 15:15:49
问题 This must be the most common problem among people new to VHDL, but I don't see what I'm doing wrong here! This seems to conform to all of the idioms that I've seen on proper state machine design. I'm compiling in Altera Quartus 9.2, for what it's worth. The actual error is: "Can't infer register for "spiclk_out" at [file] [line] because it does not hold its value outside the clock edge" ENTITY spi_state_machine IS PORT( spiclk_internal : IN STD_LOGIC; reset : IN STD_LOGIC; spiclk_out : BUFFER

Altera Quartus falsly says Modelsim isn't installed

由 喜你入骨 提交于 2019-12-08 15:56:01
问题 Installed Quartus 13.0 with Modelsim in Fedora 22 64-bit. Running Quartus in 32-bit because I get lots and lots of problems otherwise. However, I can start Quartus, create a project, synthesize it, fire up the simulation window and configure the in signals. Then, when clicking the button for launching Modelsim, it starts doing it's job, but ends up with ModelSim-Altera was not found. Please install ModelSim-Altera which is included with the Quartus II installer, or use the Quartus II

VHDL - Incrementing Register Value on Push Button Event

由 落爺英雄遲暮 提交于 2019-12-06 07:01:14
I am very new to VHDL and am trying to figure out how to do something fairly basic on an Altera Cyclone II. The FPGA has four push buttons - two of them need to be programmed to increase and decrease the selected register (0-F), and the two need to be programmed to increase and decrease the value (from 00 to FF) that will be in that register. Here is what I have so far: entity raminfr is port ( clk : in std_logic; we : in std_logic; a : in unsigned(3 downto 0); di : in unsigned(7 downto 0); do : out unsigned(7 downto 0) ); end raminfr; architecture rtl of raminfr is type ram_type is array (0

VDHL sfixed decoding code does not work properly

由 Deadly 提交于 2019-12-04 06:19:46
问题 I am using David bishop's fixed point library to do some math in vhdl. and i need to decode the final value into integers. the method i have followed as below, and i do get fine value for fractional part but the decimal value is not correct. i could not find the issue yet. in decimal part 1st two digits are wrong. xx 8374.839923 xx numbers are wrong always. when i perform this, i get 2 74334.738295 for 1 74334.738295 inside architecture, inside process i do declare these variables, variable

compiler errors when compiling *.vhdl into a library - Altera Quartus II

由 自作多情 提交于 2019-12-02 10:31:09
I've downloaded the floating point package from http://www.vhdl.org/fphdl/ and did the following: I included the math_utility_pkg.vhd, fixed_pkg_c.vhd and float_pkg_c.vhd files in my project I assigned them to a library (following the instructions in Compiling *.vhdl into a library, using Altera Quartus II ) tried to compile them, first by setting my project's top entity as top entity and the second time by setting float_pkg_c.vhd as top entity I'v encountered several issues: I'm not sure whether to use the ieee_proposed library name or floatfixlib, as the former is suggested in the
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