hdl

问题 In verilog I have an array of binary values. How do I take the absolute value of the subtracted values ? Verilog code: module aaa(clk); input clk; reg [7:0] a [1:9]; reg [7:0] s [1:9]; always@(posedge clk) begin s[1] = a[1] - a[2]; s[2] = a[2] - a[3]; s[3] = a[1] + a[3]; end endmodule I want my s[1] and s[2] values to be always positive . How can I do it in synthesisable verilog? I have tried using signed reg , but it shows an error. 回答1: Regardless of whether the number is signed or not twos

问题 I noticed that Verilog rounds my real number results into integer results. For example when I look at simulator, it shows the result of 17/2 as 9. What should I do? Is there anyway to define something like a: output real reg [11:0] output_value ? Or is it something that has to be done by simulator settings? Simulation only (no synthesis). Example: x defined as a signed input and output_value defined as output reg. output_value = ((x >>> 1) + x) + 5; If x=+1 then output value has to be: 13/2=6

问题 I am trying to implement a simple event based Verilog simulator in Python, but I actually struggle to find some details in the specification (section 11 of IEEE 1364-2005). Let's say I just perfomed an update event on clk which now obtained the new value 1 (0 before). According to the specification this requires me to schedule 'evaluation events' for sensitive processes. Do I have to schedule the evaluation of an always @(posedge clk) block as active or inactive event? I'm guessing that the

问题 I've been stuck at this problem for some hours now, and it seems I can't find the solution by searching i.e. didn't find anything here or on Google. Here's my piece of code: LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.numeric_std; USE work.arrays.ALL; ENTITY parallel IS PORT (clk:IN std_logic; text:IN INT_ARRAY(119 DOWNTO 0); result:OUT INT_MATRIX_2D); END parallel; ARCHITECTURE arch OF parallel IS COMPONENT unit_comparator IS PORT (letter:IN integer; difference:OUT integer); END

问题 What is the difference between a reg and a wire? When are we supposed to use reg and when are we supposed to use wire in a verilog module. I have also noticed sometimes that a output is declared again as a reg. E.g reg Q in a D flip flop. I have read this somewhere - "The target output of procedural assignment statements must be of reg data type." What are procedural assignment statements? I have throughly googled this but was not able to find a clear explanation. 回答1: Wire:- Wires are used

问题 What is the difference between a reg and a wire? When are we supposed to use reg and when are we supposed to use wire in a verilog module. I have also noticed sometimes that a output is declared again as a reg. E.g reg Q in a D flip flop. I have read this somewhere - "The target output of procedural assignment statements must be of reg data type." What are procedural assignment statements? I have throughly googled this but was not able to find a clear explanation. 回答1: Wire:- Wires are used

问题 In the following VHDL code when i use logical or the code stops working the HD44780LCD crashes but when i remove the logical or and remove one of the holders the code starts to work again. I'm using Xilinx Spartan 3E starter board. In other words when I replace the SendCommand <= Holder(0); with SendCommand <= Holder(0) or Holder(1); The program acts weird and crashes. Here is the code: library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_ARITH.all; use IEEE.STD_LOGIC_UNSIGNED.all;

问题 We are implementing an Ethernet MAC controller in VHDL.. To start of, here is a code snippet of my code.. -- next state PROCESS(p_state, phy_start, phy_ctr, phy_clk) BEGIN CASE p_state IS WHEN sIDLE => IF(phy_start = '1' or rising_edge(phy_start)) THEN n_state <= sPRE; ELSIF(phy_start'event AND phy_start='0') THEN n_state <= n_state; ELSE n_state <= sIDLE; END IF; ............ The problem is that my professor told me I associated phy_start as the clock signal where in the rising_edge() must

问题 I am trying to implement a one bit counter using structural VHDL and components. I am getting a syntax error when trying to do the port map. The error is "Error (10028): Can't resolve multiple constant drivers for net "P" at Assign4.vhd(47)" Here is what I have so far: Thank you in advance for any ideas. library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; -------------------------------------------------------------- Entity Assign4 is Generic (bits: POSITIVE := 1);

问题 I want to write a module in RAM and then read from the same into another module. How can I do this? I think there must be a way to pass RAM modules by referencing to other modules. For example: In module A: // write in ram and pass to module B ram ram_ins(); ram_ins.wr_en = 1; ram_ins.addr = 1; ram_ins.data_in = 1234; B b_ins(ram_ins); // pass by reference the ram_ins to the module B In module B: // read from ram ram_ins.addr = 1; reg [7:0] a; assign a = ram_ins.data_out Register a in module