Syntax error in VHDL | 易学教程

问题

I am trying to implement a one bit counter using structural VHDL and components. I am getting a syntax error when trying to do the port map. The error is "Error (10028): Can't resolve multiple constant drivers for net "P" at Assign4.vhd(47)" Here is what I have so far: Thank you in advance for any ideas.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------------------------
Entity Assign4 is
      Generic (bits: POSITIVE := 1);
      Port (CLK: in std_logic;
            SE1,SE2: in std_logic;
            P: out std_logic);
End Entity Assign4;
---------------------------------------------------------------
Architecture Structural of Assign4 is 
--------------------------------
Component Counter is
--    Generic (N: Positive := 1);
    Port(clock,sel1,sel2: in std_logic;
         Q: out std_logic);
End Component;
--------------------------------
Signal x,y,z: std_logic;

begin
P <= x;
--Qn <= x;
  process(CLK)
  begin
    if (Clk'event and CLK = '1') then
        x <= x xor (SE1 and SE2);

    end if;
  end process;

--------------COUNTER-------------------------------------
count1: Counter PORT MAP (clk,SE1,SE2,P);
---------------END COUNTER--------------------------------


-- The generate will be used later for implementing more bits in the counter
--gen: FOR i IN 0 TO 1 GENERATE
--  count1: Counter PORT MAP (SE1 <= inbits(0),SE2 <= inbits(1),clock <= CLK, 
--                            outA <= SE1 and SE2, q <= outA xor  q);
--end GENERATE gen;

---------------------------------------------------

end Architecture;

回答1:

The error message is fairly self-explanatory: you are driving P from two different places:

P <= x;

and

count1: Counter PORT MAP (clk, SE1, SE2, P);

(In the Counter component, you've listed the last port as an output, so it is driving P also.)

I cannot say which statement you want, though likely it is the latter; you'll want to comment out the first assignment, which will resolve this compilation error.

回答2:

in port map statements, the syntax is

label: componentName PORT MAP (componentSig => externalSig, ...)

your arrows are pointing the wrong way.

来源：https://stackoverflow.com/questions/5073519/syntax-error-in-vhdl

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