fpga

Use of For loop in always block

由 六眼飞鱼酱① 提交于 2019-12-25 04:12:06
问题 I am writing a Verilog code for calculating the number of digits in a decimal number. In the code below I have initialised the value of c to be equal to a. I was able to get the simulation results correctly but unable to syntesise and the error is due to 'c=a'. How can I get rid of the error ? Is there any other logic to calculate the number of digits ? Error: [Synth 8-3380] loop condition does not converge after 2000 iterations Code :- module numdigits(a,b); parameter n=100; input [0:n-1] a;

Incorrect UDP data reception in Matlab

由 雨燕双飞 提交于 2019-12-25 03:19:26
问题 My FPGA is continuously sending UDP packets on network using 10/100/1000 Mbps ethernet and i have written a MATLAB code to capture the data. FPGA kit is connected to a 1 gbps switch and then to PC. The problem is that after a certain number of packets (around 1080000 Bytes) are received in Matlab, the next packets that are received are corrupted although the FPGA is sending correct data which i have verified by running Matlab with Wireshark. 1) Does it have something to do with the fact that

VHDL: Type of “variable” is incompatible with type of <=

由 ▼魔方 西西 提交于 2019-12-25 02:09:00
问题 Could some explain why i get syntax error with this piece of code.. An <= "1110" when anode = "00" else AN <= "1101" when anode = "01" else An <= "1011" when anode = "10" else An <= "0111" when anode = "11"; segment <= counter_1r when anode = "00" else segment <= counter_10r when anode = "01" else segment <= counter_100r when anode = "10" else segment <= counter_1000r When anode = "11"; it says ERROR:HDLParsers:800 - "C:/.Xilinx/Stopur/main.vhd" Line 181. Type of An is incompatible with type

pwm generation using fpga

由 孤人 提交于 2019-12-25 01:39:35
问题 How to generate a PWM signal using an FPGA? Which is best method to generate a variable duty cycle? I tried to solve this problem by using the following code but two or three errors occurred. This is my code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use ieee.numeric_std.all; --use ieee.float_pkg.all; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use

Why dynamic power consumption is always zero?

由 |▌冷眼眸甩不掉的悲伤 提交于 2019-12-24 21:55:27
问题 I want to get an accurate power report that contains real dynamic and static power consumption. I'm working on Xilinx spartan3 board. My code has no errors but after selecting the "Generate Text Power Report" in ISE (Xilinx synthesis tool), always the power report shows that my design has no dynamic power consumption. (Why?) Power report : Dynamic = 0.00 Quiescent = 59.84 Total = 59.84 My code : LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY SRAM IS PORT( clk : IN std_logic; wr : IN std

IIC总线的FPGA实现

由 余生颓废 提交于 2019-12-24 19:13:02
一、摘要 　　DE2_TV中，有关于寄存器的配置的部分，采用的方法是通过IIC的功能，这里对IIC总线的FPGA实现做个说明。 二、实验平台 　　软件平台：ModelSim-Altera 6.4a (Quartus II 9.0) 　　硬件平台：DIY_DE2 三、实验原理 1、 IIC 总线器件工作原理 　　在IIC总线上传送信息时的时钟同步信号是由挂接在SCL时钟线上的所有器件的逻辑“与”完成的。SCL线上由高电平到低电平的跳变将影响到这些器件，一旦某个器件的时钟信号变为低电平，将使SCL线上所有器件开始并保护低电平期。此时，低电平周期短的器件的时钟由低至高的跳变并不影响SCL线的状态，这些器件将进入高电平等待的状态。 　　当所有器件的时钟信号都变为高电平时，低电平期结束，SCL线被释放返回高电平，即所有的器件都同时开始它们的高电平期。其后，第一个结束高电平期的器件又将SCL线拉成低电平。这样就在SCL线上产生一个同步时钟。可见，时钟低电平时间由时钟低电平期最长的器件决定，而时钟高电平时间由时钟高电平期最短的器件决定。 　　IIC总线上数据的传输速率在标准模式下可达100kbit/s 在快速模式下可达400kbit/s 在高速模式下可达3.4Mbit/s ，连接到总线的接口数量只由总线电容是400pF 的限制决定。 2、IIC 总线的传输协议与数据传送时序 （1）起始和停止条件

How to change timescale of VCD file dumped?

由 和自甴很熟 提交于 2019-12-24 17:28:30
问题 I'm trying to use Chisel on a "real-world" project and I'm writing the testbench code part in C++. That work well, I can see all my dumped signals in the dump.vcd file with gtkwave. But I have a problem for timescale, by default, the function module->dump() record signal with timescale at 1ps: $timescale 1ps $end Do you know how to change it ? The only way I found to change it in the testbench C++ code is to re-open the vcd after closing it and modify the first line : #define CYCLE_PERIOD_NS

How can I share and use just one RAM module in multiple modules?

由 浪子不回头ぞ 提交于 2019-12-24 16:50:13
问题 I want to write a module in RAM and then read from the same into another module. How can I do this? I think there must be a way to pass RAM modules by referencing to other modules. For example: In module A: // write in ram and pass to module B ram ram_ins(); ram_ins.wr_en = 1; ram_ins.addr = 1; ram_ins.data_in = 1234; B b_ins(ram_ins); // pass by reference the ram_ins to the module B In module B: // read from ram ram_ins.addr = 1; reg [7:0] a; assign a = ram_ins.data_out Register a in module

Altera FPGA hardware (has an issue) vs ModelSim simulation (ok) - self implemented UART

由 本秂侑毒 提交于 2019-12-24 15:40:56
问题 I have an issue with self implemented UART in VHDL. I wrote VHDL code which generates proper waveform when running on Altera ModelSim: UART.vhd: LIBRARY ieee; USE ieee.std_logic_1164.all; use ieee.numeric_std.ALL; entity UART is port ( clk_10mhz: in STD_LOGIC; uart_clk: out STD_LOGIC; txPin: out STD_LOGIC ); end entity; architecture Test of UART is signal txStart: STD_LOGIC := '0'; signal txIdle: STD_LOGIC; signal txData: STD_LOGIC_VECTOR(7 downto 0); component TX is port ( clk_in: in STD

PCIe interrupt routing

由 血红的双手。 提交于 2019-12-24 13:38:23
问题 I am currently implementing a PCIE endpoint device in xilinx PFGA, and have some problem regards to the interrupt. when the driver init, it map the interrupt to IRQ 32 [ 1078.938669] alloc irq_desc for 32 on node -1 [ 1078.938670] alloc kstat_irqs on node -1 [ 1078.938675] pci 0000:06:00.0: PCI INT A -> GSI 32 (level, low) -> IRQ 32 However, when the interrupt fires, [ 1134.850064] irq 16: nobody cared (try booting with the "irqpoll" option) [ 1134.850067] Pid: 0, comm: swapper Tainted: P 2.6
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