VHDL: Type of “variable” is incompatible with type of

问题

Could some explain why i get syntax error with this piece of code..

An <= "1110" when anode = "00" else
AN <= "1101" when anode = "01" else
An <= "1011" when anode = "10" else 
An <= "0111" when anode = "11";

segment <= counter_1r    when anode = "00" else
segment <= counter_10r   when anode = "01" else
segment <= counter_100r  when anode = "10" else
segment <= counter_1000r When anode = "11";

it says

ERROR:HDLParsers:800 - "C:/.Xilinx/Stopur/main.vhd" Line 181. Type of An is incompatible with type of <=.
ERROR:HDLParsers:800 - "C:/.Xilinx/Stopur/main.vhd" Line 182. Type of An is incompatible with type of <=.
ERROR:HDLParsers:800 - "C:/.Xilinx/Stopur/main.vhd" Line 183. Type of An is incompatible with type of <=.
ERROR:HDLParsers:800 - "C:/.Xilinx/Stopur/main.vhd" Line 181. Type of An is incompatible with type of <=.
ERROR:HDLParsers:800 - "C:/.Xilinx/Stopur/main.vhd" Line 182. Type of An is incompatible with type of <=.
ERROR:HDLParsers:800 - "C:/.Xilinx/Stopur/main.vhd" Line 183. Type of An is incompatible with type of <=.
ERROR:HDLParsers:800 - "C:/.Xilinx/Stopur/main.vhd" Line 186. Type of segment is incompatible with type of <=.
ERROR:HDLParsers:800 - "C:/.Xilinx/Stopur/main.vhd" Line 187. Type of segment is incompatible with type of <=.
ERROR:HDLParsers:800 - "C:/.Xilinx/Stopur/main.vhd" Line 188. Type of segment is incompatible with type of <=.
ERROR:HDLParsers:800 - "C:/.Xilinx/Stopur/main.vhd" Line 186. Type of segment is incompatible with type of <=.
ERROR:HDLParsers:800 - "C:/.Xilinx/Stopur/main.vhd" Line 187. Type of segment is incompatible with type of <=.
ERROR:HDLParsers:800 - "C:/.Xilinx/Stopur/main.vhd" Line 188. Type of segment is incompatible with type of <=.

Which i Don't understand, because In my code i've set all the affected element in my entity to be output, they are all using the same type.

PORT(
    CLK: in std_logic;
--  LED: out std_logic_vector (7 downto 0);
--  Switch: in std_logic_vector(7 downto 0);
    Segment: out std_logic_vector (7 downto 0); 
    AN: out std_logic_vector (3 downto 0) 
);
end Main;

architecture Behavioral of Main is
    signal counter_1000:  integer range 0 to 9;
    signal counter_100:   integer range 0 to 9;
    signal counter_10:    integer range 0 to 9;
    signal counter_1:     integer range 0 to 9;
    signal counter_1r:    std_logic_vector(7 downto 0);
    signal counter_10r:   std_logic_vector(7 downto 0);
    signal counter_100r:  std_logic_vector(7 downto 0);
    signal counter_1000r: std_logic_vector(7 downto 0);
    signal prescaler:     integer range 0 to 50000000;
    signal limit:         integer range 0 to 50000000;
    signal Anode:         std_logic_vector(1 downto 0);
begin

回答1:

To see why you get the error message, look at your code like this:

An <= "1110" when anode = "00" else (AN <= "1101")....

The else clause will be compiled as a comparison of AN with 1101 to see if it's less-than-or-equal-to. Which is of type boolean, which is incompatible with the type of An, a vector. (I wish VHDL hadn't picked <= as an assignment operator, but there we are!)

The syntax you need is more like this (note the lack of <= on the other lines)

An <= "1110" when anode = "00" else
      "1101" when anode = "01" else
      "1011" when anode = "10" else    
      "0111" when anode = "11" else
      null;

回答2:

Conditional Signal Assignment (outside of a process) is written as:

An <=
    "1110" when anode = "00" else
    "1101" when anode = "01" else
    "1011" when anode = "10" else 
    "0111" when anode = "11" else
    "0000";

segment <=
    counter_1r    when anode = "00" else
    counter_10r   when anode = "01" else
    counter_100r  when anode = "10" else
    counter_1000r When anode = "11" else
    "00000000";

Inside of a process, you will either need to use an if statement or a case statement.

来源：https://stackoverflow.com/questions/22282539/vhdl-type-of-variable-is-incompatible-with-type-of

标签

vhdl

fpga

VHDL: Type of “variable” is incompatible with type of <=

问题

回答1:

回答2: