fpga | 易学教程

Verilog Placement Constraints with Generate Statements

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问题 I'm trying to generate an array of latches that are placed adjacent to each other using a Generate statement. I've been trying to use the Xilinx constraint "RLOC" to do this, but I haven't been successful. The code below won't successfully implement, but should illustrate what I'm trying to obtain. The issue with the code below is that "i" in the constraint call isn't being converted into a string, which is what the call is looking for. Does anyone have experience doing this? I'm using a

GHDL simulator doesn't support vhdl attributes without error?

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问题 I wrote some vivado RTL and then added some vhdl attributes to the ports of the entity to define the interface to Xilinx Vivado tool as follows: library ieee; use ieee.std_logic_1164.all; entity vivado_rtl_island is port( -- Clocks i_m50_clk :in std_logic; i_m50_rst :in std_logic; -- APB Command Inteface s_paddr :in std_logic_vector(31 downto 0); s_psel :in std_logic; s_penable :in std_logic; s_pwrite :in std_logic; s_pwdata :in std_logic_vector(31 downto 0); s_pready :out std_logic; s_prdata

Difference in initializing a state machine between a simulator and synthesizer

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问题 My question is regarding the first state used in a synthesized state machine. I'm working with a Lattice iCE40 FPGA, the EDA Playground for simulation and Lattice's Diamond Programmer for synthesizing. In the following example I am generating a series of signals (the example only shows the lines referring to the state machine). This works fine in simulation; i.e. the first case accessed is sm_init_lattice and the required signals are produced). However, the synthesized version goes straight

FPGA学习笔记——点亮LED

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软件平台：win7（64bit） + Quartus II 9.1 (64-Bit) 硬件平台：东理电子Easy-FPGA Cyclone II EP2C5T114C8N 这个开发板买了很长时间了，买来后一直放那，下面来一个点灯的例子。 1. 实验任务点亮发光二极管。通过这个实验，熟悉并掌握 CPLD/FPGA 开发软件 Quartus II 的使用方法和开发流程以及 Verilog HDL 的编程方法。 2. 实验环境软件实验环境为 Quartus II 9.1 开发软件。 3. 实验原理 FPGA 器件同单片机一样，为用户提供了许多灵活的独立的输入/输出 I/O 口（单元）。 FPGA 每个 I/O 口可以配置为输入、输出、双向、集电极开路和三态门等各种组态。作为输出口时， FPGA 的 I/O 口可以吸收最大为 24mA 的电流，可以直接驱动发光二极管 LED 等器件。图 1. 1 为 8 个发光二极管硬件原理图。通过原理图可知如果要点亮这八个 LED，所以只要正确分配并锁定引脚后，在相应的引脚上输出相应低电平“ 0”，就可实现点亮该发光二极管的功能。图 1. 1 发光二极管 LED 硬件原理图 4. 实验程序 (1) 利用连续赋值 assign 语句来实现（文件名 led_test.v） module led_test (led);

Using C programming to call VHDL implementation

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问题 I'm thinking about writing a C function which basically passes an array/vector of real numbers to a VHDL implementation as an argument and the VHDL code does some computation using the array in a FPGA and returns the result back to the C function. So, my question - How do I go about writing a C function to call the VHDL implementation? Can anyone guide me in the right direction like a tutorial,API or anything? Any help will be appreciated. Thanks! :) 回答1: VHDL does not result in a run time

基于FPGA的图像处理（一）--System Generator介绍

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计算机视觉系统通常需要进行大量的信息处理才能够得到所需要的信息。目前主要有CPU、GPU、ASIC、DSP、FPGA等计算平台。常用的计算机视觉系统通过通用计算机进行视觉信息处理，但是，由于CPU的计算能力有限，对于一些计算复杂度很高的视觉算法，其处理速度常常难以满足系统的实时性需要。 GPU具有高度的并行计算能力，可以较好地解决计算速度的问题，然而，基于GPU的计算机视觉系统存在着功耗较高、体积较大的缺点，难以满足依靠自身所带电池供电并长时间工作的服务机器人等应用系统的需要。利用专用集成电路ASIC实现视觉处理算法，可以解决视觉系统性能和体积、功耗之间的矛盾，是高性能嵌入式视觉系统的一种有效的解决方案。然而，ASIC开发周期长、修改不方便，通用性较差。 FPGA可以通过编程方便地修改其内部的逻辑功能，从而实现高速的硬件计算和并行运算，是高性能嵌入式视觉系统的一种更加方便的解决方案。基于FPGA的嵌入式视觉系统的功耗远远低于基于CPU和GPU的视觉系统，FPGA的功耗通常不到1W，而高性能CPU和GPU的功耗通常都在100W以上。随着技术的不断进步，FPGA的集成度越来越高，可以实现的设计规模越来越大，而功耗则越来越低。因此，基于FPGA的嵌入式视觉系统将是计算机视觉系统的重要发展方向。使用FPGA进行图像处理时，既要对赢家有很深的了解，同时又需要对图像处理的算法很熟悉

VHDL - Incrementing Register Value on Push Button Event

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问题 I am very new to VHDL and am trying to figure out how to do something fairly basic on an Altera Cyclone II. The FPGA has four push buttons - two of them need to be programmed to increase and decrease the selected register (0-F), and the two need to be programmed to increase and decrease the value (from 00 to FF) that will be in that register. Here is what I have so far: entity raminfr is port ( clk : in std_logic; we : in std_logic; a : in unsigned(3 downto 0); di : in unsigned(7 downto 0);

VHDL - Incrementing Register Value on Push Button Event

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Seven Segment Multiplexing on Basys2

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问题 this is my first post so I hope I'm doing this correctly. I'm trying to output a "4 3 2 1" on a four digit seven segment display on a BASYS2 board. I have checked to make sure that 0 enables the signal and that I have the ports mapped correctly. I believe the error is within my multiplexing logic since I am only able to display a single digit. I'm new to Verilog (am used to C) and would appreciate any suggestions. Thanks `timescale 1ns / 1ps module main (clock, AN0, AN1, AN2, AN3, CA, CB, CC,

基于FPGA的有限状态机浅析

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　　前言：状态机大法好，状态机几乎可以实现一切时序逻辑电路。有限状态机（Finite State Machine， FSM），根据状态机的输出是否与输入有关，可分为Moore型状态机和Mealy型状态机。Moore型状态机输出仅仅与现态有关和Mealy型状态机不仅与现态有关，也与输入有关，所以会受到输入的干扰，可能会产生毛刺（Glith）的现象，所以我们通常使用的是Moore型状态机。状态机的编码，二进制编码（Binary），格雷码编码（Gray-code），独热码（One-hot）。不同的编码方式是防止在状态转移中发生突变，使得状态转移更为稳定，系统更加可靠，但是通常情况下我们直接采用的是二进制进行编码，除非系统对稳定性和状态编码有特殊要求。状态机的描述，一段式、二段式、三段式。一段式状态机，将组合逻辑和时序逻辑混合在一起，这样的写法对于逻辑简单的状态机来说还是可以使用的，但是对于复杂的逻辑就不推荐了，如果状态复杂也会容易出错，而且一个always块中信号太多也不利于维护和修改。 1 //状态参数声明 2 parameter S0 = 4'b0000, 3 S1 = 4'b0001, 4 s2 = 4'b0010; 5 //FSM one segment 6 reg [3:0] state; 7 always @(posedge clk or negedge rst_n

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