fpga | 易学教程

Seven Segment Display outputs are unknown

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问题 I'm trying to make a counter that counts from 0-9 and displays on my Nexys A7's seven segment display. The code compiles, but in the testbench it shows that all the outputs are unknown. I tested my clock divider module, and it looks fine. I'm not sure why it isn't working. module BCD_sevenseg( input clk, output segA, segB, segC, segD, segE, segF, segG, segDP, div_clk ); counter module1( .clk(clk), .div_clk(div_clk) ); reg[3:0] BCD; //BCD signal is 4 bits wide always@(posedge clk) //check

NI Labview FPGA: ERROR:Portability:3 - Xilinx Application has run out of memory

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问题 I am using NI Labview FPGA to compile and synthesise a design onto the FPGA and have encountered the following error: LabVIEW FPGA: The compilation failed due to a Xilinx error. Details: ERROR:Portability:3 - This Xilinx application has run out of memory or has encountered a memory conflict. Current memory usage is 4025524 kb. You can try increasing your system's physical or virtual memory. If you are using a Win32 system, you can increase your application memory from 2GB to 3GB using the /3G

serial monitoring method to test communication via com ports without a serial communication device

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问题 I have a Verilog code simulated and synthesized on ISE design toolkit. I've got an FPGA spartan 6 device which is to be used for the implementation. But there is a problem with the device (probably a power issue) which makes the device unavailable in any of the COM ports when I connected it to my PC. So I want to check whether my Matlab code which I made for serial communication through the device does the desired job. So I need a method to test serial communication via any of the COM ports

Programming FPGA with DPDK

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问题 I'm facing a problem: there is a need to create a simple firewall to cut unwanted packets directly on FPGA. Basically the idea is to have a shared table with rules. This table is meant to be accessed from FPGA to check whether to pass a packet or not and it's populated by an app from userspace. I've heard of DPDK project that can handle packet processing. But I couldn't find any info how to make it work on FPGA. Is it possible? Are there any recommendations on solving the problem? 回答1: DPDK

Sending DATA to FPGA

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问题 I am working on a project which requires data to be sent FROM PC TO FPGA,which processes the data and sends it BACK TO PC. The board I am using is Atlys™ Spartan-6 FPGA Development Board. The data is to be sent as 1 byte , because 1 byte is processed at each rising edge of the clock. Could you please suggest me ways of sending data to FPGA ? Thanks 回答1: Pick some method of communication that you have access to IP (intellectual property) cores for. For example, if you can readily access a UDP

Sending DATA to FPGA

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VHDL buffer variable vs out variable

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问题 I work in a VHDL program and I need to do a RAM 256 using the ALTERA DE2-115. The outputs will show in a seven segment display. The problem is that: I have a dataout output variable. Then the variable has the following values of the temp_ram array: dataout <= temp_ram(conv_integer(dir)); Then I want to divide the vaules of dataout to put in the seven segment dataout(7 downto 4) dataout(3 downto 0) This shows the following error: Error (10309): VHDL Interface Declaration error in RAM.vhd(45):

How to use DS18B20 temperature sensor (1 Wire Communication )? [closed]

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问题 Closed . This question needs to be more focused. It is not currently accepting answers. Want to improve this question? Update the question so it focuses on one problem only by editing this post. Closed 9 days ago . Improve this question We are using a DS18B20 temperature sensor (1 Wire Communication ) .The Sensor has 3 interfaces VCC,GND , and output in Digital formant How can we display the Output on the 7 segment Display . Should we use STD_LOGIC_VECTOR ?.Note : We will be using an FPGA not

How to use DS18B20 temperature sensor (1 Wire Communication )? [closed]

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Utilities Zynq in a PL only configuration

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Is it possible to utilize Zynq in a PL-only configuration? You don’t need to have the ARM instantiated in your design but nevertheless the ARM is always present to take care of the configuration task. The Boot ROM code will always get executed at POR and the hard PS will boot. Remember, Zynq is a standalone processor and does not require PL configuration as is needed for MicroBlaze. Here is what you need to do if you are using PL only: Create an FSBL for the board (FSBL is needed for loading the bitstream). If you already have an SDK project for this board for any reference design (just make