问题
I'm facing a problem: there is a need to create a simple firewall to cut unwanted packets directly on FPGA. Basically the idea is to have a shared table with rules. This table is meant to be accessed from FPGA to check whether to pass a packet or not and it's populated by an app from userspace.
I've heard of DPDK project that can handle packet processing. But I couldn't find any info how to make it work on FPGA. Is it possible? Are there any recommendations on solving the problem?
回答1:
DPDK libraries does not pack any RTL images as reference code. In the current case, there are no firewall RTL images either in inline or lookaside mode.
A couple of FPGA variant which uses inline FPGA with Ethernet are Intel N3000 which houses Intel Arria 10 and Fortville X710 and Intel Arkville Data Mover. Link to talk in DPDK summit of the same is https://www.dpdk.org/wp-content/uploads/sites/35/2018/12/PetrKastovsky-AcceleratingDPDKviaP4-programmableFPGA-basedSmartNICs.pdf, and https://www.bittware.com/fpga/arkville/ . While DPDK IFPGA RAW PMD allows managing and RX-TX packets out from the device. Links https://doc.dpdk.org/guides-18.05/rawdevs/ifpga_rawdev.html.
hence the expectation of having DPDK to create FPGA RTL image for Firewall and program the FPGA in use is not true.
note: One can add themselves to Netwrok Builder program from Intel and get couple sample references (RTL images) which are used for similar use case like ACL firewall.
来源：https://stackoverflow.com/questions/62875872/programming-fpga-with-dpdk