computer-architecture

问题 Consider the following sequence of micro-operations. MBR ← PC MAR ← X PC ← Y Memory ← MBR Which one of the following is a possible operation performed by this sequence? Instruction fetch Operand fetch Conditional branch Initiation of interrupt service Answer is option (4). My attempt : Instruction fetch : Fetch instruction: Read instruction code from address in PC and place in IR. ( IR ← Memory[PC] ) Operand fetch : Fetch operands from memory if necessary: If any operands are memory addresses

问题 Consider the following sequence of micro-operations. MBR ← PC MAR ← X PC ← Y Memory ← MBR Which one of the following is a possible operation performed by this sequence? Instruction fetch Operand fetch Conditional branch Initiation of interrupt service Answer is option (4). My attempt : Instruction fetch : Fetch instruction: Read instruction code from address in PC and place in IR. ( IR ← Memory[PC] ) Operand fetch : Fetch operands from memory if necessary: If any operands are memory addresses

问题 Intel says after reset the processor is placed in real mode and the software initialization code starts at 0xFFFFFFF0H. My questions: If processor is in real-mode how can it acess the memory > 1MB (0xFFFFFFF0H) How this happens or what happens when RAM in < 4GB ( say 2GB) If the BIOS is mapped at 0x000FFFFFH why processor starts executing at 0xFFFFFFF0H Please help me with these questions. Thanks. 回答1: I finally found the answer in the Coreboot documentation: Whenever an x86 CPU wakes up

问题 We are taught that the abstraction of the RAM memory is a long array of bytes. And that for the CPU it takes the same amount of time to access any part of it. What is the device that has the ability to access any byte out of the 4 gigabytes (on my computer) in the same time? As this does not seem as a trivial task for me. I have asked colleagues and my professors, but nobody can pinpoint to the how this task can be achieved with simple logic gates, and if it isn't just a tricky combination of

问题 I was reading this question, I wanted to ask more about the code that he showed i.e for(i = 0; i < 20; i++) for(j = 0; j < 10; j++) a[i] = a[i]*j; The questions are, I understand temporal locality, I think that references to i and j should be temporal locality. Am I right? I also understand spatial locality, as the question I linked answers that references to a[i] should be spatial locality. Am I right? The person said, "The inner loop will call same memory address when accessing a[i] ten

问题 Before the advent of hardware assisted virtualization there were instructions that could not be virtualized due to various reasons. Can somebody please explain what those instructions are and why they cannot be virtualized? 回答1: To virtualize an ISA, certain requirements must be met. Popek and Goldberg used something like the following: A machine has at least two modes (a) user mode and (b) system mode . Typically, applications run in user mode and the operating system runs in system mode .

问题 When MCR or MRC instructions execute with different cRm or opt2 , then what is the status of cRn register? For example if run: asm volatile("mcr p15, 0, %0, c9, c13, 0" : : "r"(val)) or asm volatile("mcr p15, 0, %0, c9, c13, 2" : : "r"(val)) then, which register's value will be changed c9 or c13 ? and what is the role of last option(0 or 2)?.here 回答1: The MCR and MRC instructions are generic coprocessor instructions. What these instructions do depends on the particular hardware you're using,

问题 Hi have some question regarding spatial and temporal locality. I have read in the course theory that spatial locality If one item is referenced, the likelihood of other address close by will be referenced soon temporal locality One item that is referenced at one point in time it tend to be referenced soon again. Ok, but how do I see that in the code? I think I understood the concept for temporal locality but I don't understand spatial locality yet. For instance in this loop for(i = 0; i < 20;

问题 What forms of memory address spaces have been used? Today, a large flat virtual address space is common. Historically, more complicated address spaces have been used, such as a pair of a base address and an offset, a pair of a segment number and an offset, a word address plus some index for a byte or other sub-object, and so on. From time to time, various answers and comments assert that C/C++ pointers are essentially integers. That is an incorrect model for C/C++, since the variety of

问题 This is based off this question LEA instruction Here is the code segment I have a question about .ORIG X3700 LEA R0, A ..... A .FILL X1234 @Paul R, the answer responder, said that "The origin of the code is x3700, and you have 12 instructions, so the address of A will be x3700 + x0C = x370C. As you guessed, LEA R0,A loads the address of A into R0, so R0 will contain x370C after that first instruction has been executed." I agree with the first part of what Paul said, his reasoning for why the